Searched refs:SubIdx (Results 1 - 25 of 56) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp242 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); local
243 return TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes);
246 unsigned SubIdx = MI.getOperand(3).getImm(); local
248 TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes);
257 MO1UsedLanes = UsedLanes & ~TRI->getSubRegIndexLaneMask(SubIdx);
266 unsigned SubIdx = MI.getOperand(2).getImm(); local
267 return TRI->composeSubRegIndexLaneMask(SubIdx, UsedLanes);
316 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); local
317 DefinedLanes = TRI->composeSubRegIndexLaneMask(SubIdx, DefinedLanes);
318 DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx);
322 unsigned SubIdx = MI.getOperand(3).getImm(); local
334 unsigned SubIdx = MI.getOperand(2).getImm(); local
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H A DExpandPostRAPseudos.cpp85 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
86 unsigned SubIdx = MI->getOperand(3).getImm(); local
88 assert(SubIdx != 0 && "Invalid index for insert_subreg");
89 Register DstSubReg = TRI->getSubReg(DstReg, SubIdx);
100 MI->RemoveOperand(3); // SubIdx
113 MI->RemoveOperand(3); // SubIdx
H A DTargetRegisterInfo.cpp90 unsigned SubIdx, const MachineRegisterInfo *MRI) {
91 return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) {
111 if (SubIdx) {
113 OS << ':' << TRI->getSubRegIndexName(SubIdx);
115 OS << ":sub(" << SubIdx << ')'; local
89 printReg(Register Reg, const TargetRegisterInfo *TRI, unsigned SubIdx, const MachineRegisterInfo *MRI) argument
H A DPeepholeOptimizer.cpp460 unsigned SrcReg, DstReg, SubIdx;
461 if (!TII->isCoalescableExtInstr(MI, SrcReg, DstReg, SubIdx))
475 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx);
482 // If UseSrcSubIdx is Set, SubIdx also applies to SrcReg, and only uses of
483 // SrcReg:SubIdx should be replaced.
485 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr;
510 // Only accept uses of SrcReg:SubIdx.
511 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
588 .addReg(DstReg, 0, SubIdx);
589 // SubIdx applie
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H A DTargetInstrInfo.cpp380 unsigned SubIdx, unsigned &Size,
384 if (!SubIdx) {
389 unsigned BitSize = TRI->getSubRegIdxSize(SubIdx);
394 int BitOffset = TRI->getSubRegIdxOffset(SubIdx);
411 unsigned DestReg, unsigned SubIdx,
415 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1233 // Record Reg:SubReg, SubIdx.
1261 InputReg.SubIdx = (unsigned)MOSubIdx.getImm();
1289 InsertedReg.SubIdx = (unsigned)MOSubIdx.getImm();
379 getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const argument
409 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const argument
H A DRegisterCoalescer.cpp288 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
508 "Cannot have a physical SubIdx");
1681 unsigned SubIdx) {
1718 if (DstInt && !Reads && SubIdx && !UseMI->isDebugValue())
1728 if (SubIdx && MO.isDef())
1733 if (SubIdx != 0 && MO.isUse() && MRI->shouldTrackSubRegLiveness(DstReg)) {
1737 LaneBitmask UsedLanes = TRI->getSubRegIndexLaneMask(SubIdx);
1750 addUndefFlag(*DstInt, UseIdx, MO, SubIdx);
1756 MO.substVirtReg(DstReg, SubIdx, *TRI);
2206 /// subregister SubIdx i
1680 updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx) argument
2208 const unsigned SubIdx; member in class:__anon4631::JoinVals
2373 JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, LaneBitmask LaneMask, SmallVectorImpl<VNInfo*> &newVNInfo, const CoalescerPair &cp, LiveIntervals *lis, const TargetRegisterInfo *TRI, bool SubRangeJoin, bool TrackSubRegLiveness) argument
2865 usesLanes(const MachineInstr &MI, unsigned Reg, unsigned SubIdx, LaneBitmask Lanes) const argument
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H A DMachineOperand.cpp75 void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx, argument
78 if (SubIdx && getSubReg())
79 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
81 if (SubIdx)
82 setSubReg(SubIdx);
H A DSplitKit.h440 unsigned SubIdx, LiveInterval &DestLI, bool Late, SlotIndex Def);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.h41 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx,
H A DThumbRegisterInfo.cpp64 unsigned SubIdx, int Val,
76 .addReg(DestReg, getDefRegState(true), SubIdx)
84 unsigned SubIdx, int Val,
95 .addReg(DestReg, getDefRegState(true), SubIdx)
105 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val,
113 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred,
116 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred,
61 emitThumb1LoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) argument
81 emitThumb2LoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) argument
103 emitLoadConstPool( MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
H A DARMBaseRegisterInfo.h187 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/MC/
H A DMCRegisterInfo.cpp24 MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, argument
27 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h338 const char *getSubRegIndexName(unsigned SubIdx) const {
339 assert(SubIdx && SubIdx < getNumSubRegIndices() &&
341 return SubRegIndexNames[SubIdx-1];
345 /// SubIdx \see LaneBitmask.
347 /// SubIdx == 0 is allowed, it has the lane mask ~0u.
348 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const {
349 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
350 return SubRegIndexLaneMasks[SubIdx];
515 /// Reg so its sub-register of index SubIdx i
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H A DTargetInstrInfo.h237 /// register. This also returns the sub-register index in SubIdx.
239 unsigned &DstReg, unsigned &SubIdx) const {
340 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
368 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
369 /// SubIdx.
372 unsigned SubIdx, const MachineInstr &Orig,
469 unsigned SubIdx; member in struct:llvm::TargetInstrInfo::RegSubRegPairAndIdx
472 unsigned SubIdx = 0)
473 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
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/freebsd-12-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp134 CodeGenSubRegIndex *SubIdx = *I; local
135 SubIdx->computeConcatTransitiveClosure();
137 for (CodeGenSubRegIndex *SRI : SubIdx->ConcatenationOf)
141 if (SubIdx->ConcatenationOf.empty()) {
145 I = ConcatenationOf.insert(I, SubIdx->ConcatenationOf.begin(),
146 SubIdx->ConcatenationOf.end());
147 I += SubIdx->ConcatenationOf.size();
502 for (CodeGenSubRegIndex *SubIdx : SubRegIdx->ConcatenationOf)
503 Parts.push_back(SubIdx);
537 CodeGenSubRegIndex *SubIdx local
1068 getSuperRegClasses(const CodeGenSubRegIndex *SubIdx, BitVector &Out) const argument
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H A DCodeGenRegisters.h378 // registers have a SubIdx sub-register.
380 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const {
381 return SubClassWithSubReg.lookup(SubIdx);
384 /// Find largest subclass where all registers have SubIdx subregisters in
390 /// a class where every register has SubIdx and SubRegClass is a class where
391 /// every register is covered by the SubIdx subregister of SubClass.
394 const CodeGenSubRegIndex *SubIdx) const;
396 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, argument
398 SubClassWithSubReg[SubIdx] = SubRC;
402 // containing only SubIdx supe
407 addSuperRegClass(CodeGenSubRegIndex *SubIdx, CodeGenRegisterClass *SuperRC) argument
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H A DRegisterBankEmitter.cpp196 // More precisely, PossibleSubclass is a subreg-class iff Reg:SubIdx is in
199 for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) {
201 PossibleSubclass.getSuperRegClasses(&SubIdx, BV);
H A DCodeGenTarget.h107 /// covers \p SubIdx if it exists.
110 const CodeGenSubRegIndex *SubIdx) const;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp449 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
452 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
454 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
459 // VReg has been adjusted. It can be used with SubIdx operands now.
465 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
466 assert(RC && "No legal register class for VT supports that SubIdx");
498 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
516 SubIdx == DefSubIdx &&
528 // Reg may not support a SubIdx sub-register, and we may need to
532 Reg = ConstrainForSubReg(Reg, SubIdx,
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H A DInstrEmitter.h78 /// supports SubIdx sub-registers. Emit a copy if that isn't possible.
80 unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx, MVT VT,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp204 unsigned SubIdx = X86::NoSubRegister; local
206 SubIdx = X86::sub_32bit;
208 SubIdx = X86::sub_16bit;
210 SubIdx = X86::sub_8bit;
213 return SubIdx;
742 unsigned SubIdx; local
745 SubIdx = X86::NoSubRegister;
747 SubIdx = X86::sub_32bit;
749 SubIdx = X86::sub_16bit;
751 SubIdx
1201 unsigned SubIdx = X86::NoSubRegister; local
1239 unsigned SubIdx = X86::NoSubRegister; local
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H A DX86RegisterInfo.cpp101 unsigned SubIdx) const {
103 if (!Is64Bit && SubIdx == X86::sub_8bit) {
108 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
H A DX86InstrInfo.h182 /// SubIdx.
184 unsigned &DstReg, unsigned &SubIdx) const override;
211 unsigned DestReg, unsigned SubIdx,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp314 SDValue SubIdx = DAG.getNode(ISD::AND, dl, MVT::i32, {Idx, Mask}); local
315 return SubIdx;
681 SDValue SubIdx = getIndexInWord32(IdxV, ElemTy, DAG);
684 return extractVector(ExVec, SubIdx, dl, ElemTy, MVT::i32, DAG);
742 SDValue SubIdx = getIndexInWord32(IdxV, ElemTy, DAG); local
745 ValV, SubIdx, dl, ElemTy, DAG);
780 unsigned SubIdx; local
782 SubIdx = Hexagon::vsub_hi;
785 SubIdx = Hexagon::vsub_lo;
788 VecV = DAG.getTargetExtractSubreg(SubIdx, d
903 unsigned SubIdx = (Idx == 0) ? Hexagon::vsub_lo : Hexagon::vsub_hi; local
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.h82 unsigned SubIdx) const;

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