Searched refs:SrcReg2 (Results 1 - 20 of 20) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.h95 // SrcReg2 if having two register operands, and the value it compares against
98 unsigned &SrcReg2, int &CmpMask,
105 unsigned SrcReg2, int CmpMask, int CmpValue,
H A DLanaiInstrInfo.cpp178 unsigned &SrcReg2, int &CmpMask,
186 SrcReg2 = 0;
192 SrcReg2 = MI.getOperand(1).getReg();
206 unsigned SrcReg2, int ImmValue,
211 OI->getOperand(2).getReg() == SrcReg2) ||
212 (OI->getOperand(1).getReg() == SrcReg2 &&
284 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int /*CmpMask*/,
304 if (SrcReg2 != 0)
330 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
382 if (SrcReg2 !
177 analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const argument
205 isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg, unsigned SrcReg2, int ImmValue, MachineInstr *OI) argument
283 optimizeCompareInstr( MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int , int CmpValue, const MachineRegisterInfo *MRI) const argument
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZElimCompare.cpp627 // SrcReg2 is the register if the source operand is a register,
631 Register SrcReg2 = local
636 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI)))
684 // Clear any intervening kills of SrcReg and SrcReg2.
688 if (SrcReg2)
689 MBBI->clearRegisterKills(SrcReg2, TRI);
H A DSystemZInstrInfo.h223 unsigned &SrcReg2, int &Mask, int &Value) const override;
H A DSystemZInstrInfo.cpp517 unsigned &SrcReg2, int &Mask,
524 SrcReg2 = 0;
516 analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h206 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
209 unsigned &SrcReg2, int &CmpMask,
214 unsigned SrcReg2, int CmpMask, int CmpValue,
H A DAArch64SIMDInstrOpt.cpp438 Register SrcReg2 = MI.getOperand(3).getReg(); local
444 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) {
447 .addReg(SrcReg2, Src2IsKill)
H A DAArch64InstrInfo.cpp985 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
988 unsigned &SrcReg2, int &CmpMask,
1013 SrcReg2 = MI.getOperand(2).getReg();
1022 SrcReg2 = 0;
1032 SrcReg2 = 0;
1183 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask,
1213 if (CmpValue != 0 || SrcReg2 != 0)
4184 unsigned SrcReg2; local
4188 SrcReg2 = *ReplacedAddend;
4191 SrcReg2
1182 optimizeCompareInstr( MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const argument
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp857 unsigned SrcReg2 = 0; local
859 SrcReg2 = getRegForValue(SrcValue2);
860 if (SrcReg2 == 0)
868 auto RC2 = SrcReg2 != 0 ? MRI.getRegClass(SrcReg2) : nullptr;
891 SrcReg2 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg2);
941 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
943 SrcReg2 = ExtReg;
949 .addReg(SrcReg1).addReg(SrcReg2);
1359 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); local
[all...]
H A DPPCInstrInfo.h352 unsigned &SrcReg2, int &Mask, int &Value) const override;
355 unsigned SrcReg2, int Mask, int Value,
H A DPPCInstrInfo.cpp1591 unsigned &SrcReg2, int &Mask,
1602 SrcReg2 = 0;
1613 SrcReg2 = MI.getOperand(2).getReg();
1621 unsigned SrcReg2, int Mask, int Value,
1727 if (SrcReg2 != 0)
1802 Instr.getOperand(2).getReg() == SrcReg2) ||
1803 (Instr.getOperand(1).getReg() == SrcReg2 &&
1849 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
4129 Register SrcReg2
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.h469 /// in SrcReg and SrcReg2 if having two register operands, and the value it
473 unsigned &SrcReg2, int &CmpMask,
480 unsigned SrcReg2, int CmpMask, int CmpValue,
H A DX86InstrInfo.cpp1053 Register SrcReg2; local
1056 SrcReg2, isKill2, ImplicitOp2, LV))
1065 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1067 LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
3274 unsigned &SrcReg2, int &CmpMask,
3286 SrcReg2 = 0;
3300 SrcReg2 = 0;
3309 SrcReg2 = MI.getOperand(2).getReg();
3321 SrcReg2 = 0;
3334 SrcReg2
3273 analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const argument
3360 isRedundantFlagInstr(const MachineInstr &FlagI, unsigned SrcReg, unsigned SrcReg2, int ImmMask, int ImmValue, const MachineInstr &OI) argument
3550 optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const argument
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DPeepholeOptimizer.cpp610 unsigned SrcReg, SrcReg2; local
612 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
614 (SrcReg2 != 0 && Register::isPhysicalRegister(SrcReg2)))
618 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp2671 /// in SrcReg and SrcReg2 if having two register operands, and the value it
2675 unsigned &SrcReg2, int &CmpMask,
2683 SrcReg2 = 0;
2691 SrcReg2 = MI.getOperand(1).getReg();
2698 SrcReg2 = 0;
2746 unsigned SrcReg, unsigned SrcReg2,
2752 OI->getOperand(2).getReg() == SrcReg2) ||
2753 (OI->getOperand(1).getReg() == SrcReg2 &&
2761 OI->getOperand(3).getReg() == SrcReg2) ||
2762 (OI->getOperand(2).getReg() == SrcReg2
2674 analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const argument
2745 isRedundantFlagInstr(const MachineInstr *CmpI, unsigned SrcReg, unsigned SrcReg2, int ImmValue, const MachineInstr *OI, bool &IsThumb1) argument
2881 optimizeCompareInstr( MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const argument
3169 unsigned SrcReg, SrcReg2; local
[all...]
H A DARMFastISel.cpp1428 unsigned SrcReg2 = 0; local
1430 SrcReg2 = getRegForValue(Src2Value);
1431 if (SrcReg2 == 0) return false;
1439 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1440 if (SrcReg2 == 0) return false;
1447 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);
1449 .addReg(SrcReg1).addReg(SrcReg2));
1776 unsigned SrcReg2 local
[all...]
H A DARMBaseInstrInfo.h286 /// in SrcReg and SrcReg2 if having two register operands, and the value it
290 unsigned &SrcReg2, int &CmpMask,
298 unsigned SrcReg2, int CmpMask, int CmpValue,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h268 /// in SrcReg and SrcReg2 if having two register operands, and the value it
272 unsigned &SrcReg2, int &Mask, int &Value) const override;
H A DHexagonInstrInfo.cpp1762 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1766 unsigned &SrcReg2, int &Mask,
1827 SrcReg2 = MI.getOperand(2).getReg();
1842 SrcReg2 = 0;
1765 analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1394 /// in SrcReg and SrcReg2 if having two register operands, and the value it
1398 unsigned &SrcReg2, int &Mask, int &Value) const {
1406 unsigned SrcReg2, int Mask, int Value,
1397 analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument
1405 optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const argument

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