Searched refs:Src2Reg (Results 1 - 8 of 8) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZPostRewrite.cpp112 Register Src2Reg = MBBI->getOperand(2).getReg(); local
115 bool Src2IsHigh = SystemZ::isHighReg(Src2Reg);
120 if (DestReg != Src1Reg && DestReg != Src2Reg) {
133 Src2Reg = DestReg;
139 if (DestReg != Src1Reg && DestReg == Src2Reg) {
141 std::swap(Src1Reg, Src2Reg);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp191 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; local
325 Src2Reg = MCI.getOperand(2).getReg();
327 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) &&
333 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) &&
341 Src2Reg = MCI.getOperand(2).getReg();
343 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) &&
360 Src2Reg = MCI.getOperand(2).getReg();
362 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) &&
370 Src2Reg = MCI.getOperand(2).getReg();
371 if (HexagonMCInstrInfo::isDblRegForSubInst(Src2Reg)
[all...]
H A DHexagonMCCompound.cpp80 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; local
98 Src2Reg = MI.getOperand(2).getReg();
101 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg))
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp276 Register Src2Reg = MI->getOperand(3).getReg(); local
292 .addReg(Src2Reg, getKillRegState(Src2Kill));
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1178 Register Src2Reg = MI.getOperand(2).getReg(); local
1181 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1182 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1202 Register Src2Reg = MI.getOperand(2).getReg(); local
1206 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1207 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
3294 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; local
3310 Src2Reg = MI.getOperand(2).getReg();
3313 isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3726 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; local
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstructionSelector.cpp1103 Register Src2Reg = I.getOperand(2).getReg(); local
1110 Optional<int64_t> ImmVal = getVectorSHLImm(Ty, Src2Reg, MRI);
1129 Shl.addUse(Src2Reg);
1141 Register Src2Reg = I.getOperand(2).getReg(); local
1171 auto Neg = MIB.buildInstr(NegOpc, {RC}, {Src2Reg});
2611 Register Src2Reg = I.getOperand(3).getReg(); local
2760 std::swap(SrcReg, Src2Reg);
2763 auto Cmp = MIB.buildInstr(Opc, {SrcRC}, {SrcReg, Src2Reg});
2823 Register Src2Reg = I.getOperand(2).getReg(); local
2830 Src2Reg, /* LaneId
3779 Register Src2Reg = I.getOperand(2).getReg(); local
[all...]
H A DAArch64FastISel.cpp2694 unsigned Src2Reg = getRegForValue(Src2Val); local
2695 if (!Src2Reg)
2704 Src1IsKill, Src2Reg, Src2IsKill);
2822 unsigned Src2Reg = getRegForValue(SI->getFalseValue()); local
2825 if (!Src1Reg || !Src2Reg)
2829 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg,
2833 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1048 unsigned Src2Reg = getRegForValue(SI->getFalseValue()); local
1051 if (!Src1Reg || !Src2Reg || !CondReg)
1067 emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);

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