Searched refs:Src1Regs (Results 1 - 3 of 3) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp727 SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs; local
728 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
737 MIRBuilder.buildUAddo(DstReg, CarryOut, Src1Regs[i], Src2Regs[i]);
739 MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
762 SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs; local
763 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
769 {Src1Regs[0], Src2Regs[0]});
777 {Src1Regs[i], Src2Regs[i], BorrowIn});
2412 SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs; local
2417 extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src1Regs);
2632 SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs; local
2707 SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs; local
3398 multiplyRegisters(SmallVectorImpl<Register> &DstRegs, ArrayRef<Register> Src1Regs, ArrayRef<Register> Src2Regs, LLT NarrowTy) argument
3646 SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs; local
3692 SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs; local
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/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizerHelper.h170 ArrayRef<Register> Src1Regs,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp1590 SmallVector<Register, 2> Src1Regs(OpdMapper.getVRegs(2));
1595 assert(Src1Regs.empty() && Src2Regs.empty());
1599 if (Src1Regs.empty())
1600 split64BitValueForMapping(B, Src1Regs, HalfTy, MI.getOperand(2).getReg());
1602 setRegsToType(MRI, Src1Regs, HalfTy);
1612 B.buildSelect(DefRegs[0], CondRegs[0], Src1Regs[0], Src2Regs[0]);
1613 B.buildSelect(DefRegs[1], CondRegs[0], Src1Regs[1], Src2Regs[1]);
1670 SmallVector<Register, 2> Src1Regs(OpdMapper.getVRegs(2));
1674 assert(Src0Regs.empty() && Src1Regs.empty());
1679 assert(Src0Regs.size() == Src1Regs
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