| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsExpandPseudo.cpp | 181 const unsigned ShiftImm = local
185 .addImm(ShiftImm);
188 .addImm(ShiftImm);
557 const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24; local
560 .addImm(ShiftImm);
563 .addImm(ShiftImm);
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| H A D | MipsISelLowering.cpp | 1638 int64_t ShiftImm = 32 - (Size * 8);
1640 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1641 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 213 uint64_t ShiftImm, bool SetFlags = false,
218 uint64_t ShiftImm, bool SetFlags = false,
246 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
254 uint64_t ShiftImm);
1360 unsigned ShiftImm; local
1362 ShiftImm = 0;
1364 ShiftImm = 12;
1393 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm));
1401 uint64_t ShiftImm, bool SetFlags,
1411 if (ShiftImm >
1397 emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm, bool SetFlags, bool WantResult) argument
1440 emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, AArch64_AM::ShiftExtendType ExtType, uint64_t ShiftImm, bool SetFlags, bool WantResult) argument
1597 emitSubs_rs(MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm, bool WantResult) argument
1737 emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, uint64_t ShiftImm) argument
[all...] |
| H A D | AArch64ISelDAGToDAG.cpp | 1679 uint64_t ShiftImm; local
1680 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRL, ShiftImm) &&
1681 !isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm))
1685 if (ShiftImm + Width > BitWidth)
1690 Immr = ShiftImm;
1691 Imms = ShiftImm + Width - 1;
1703 // SRL Value2, ShiftImm
1705 // with MaskImm >> ShiftImm to search for the bit width.
1709 // UBFM Value, ShiftImm, BitWide + SrlImm -1
1816 uint64_t ShiftImm;
[all...] |
| H A D | AArch64InstructionSelector.cpp | 1066 Optional<int64_t> ShiftImm = getVectorShiftImm(Reg, MRI); local
1067 if (!ShiftImm)
1070 int64_t Imm = *ShiftImm;
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 787 unsigned ShiftImm; // shift for OffsetReg. member in struct:__anon5075::ARMOperand::MemoryOp
797 unsigned ShiftImm; member in struct:__anon5075::ARMOperand::PostIdxRegOp
809 unsigned ShiftImm; member in struct:__anon5075::ARMOperand::RegShiftedRegOp
815 unsigned ShiftImm; member in struct:__anon5075::ARMOperand::RegShiftedImmOp
1607 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1626 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1776 (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift))
2420 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
2429 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
3460 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, unsigned ShiftReg, unsigned ShiftImm, SMLoc S, SMLoc E) argument
3474 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, unsigned ShiftImm, SMLoc S, SMLoc E) argument
3625 CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm, unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S, SMLoc E, SMLoc AlignmentLoc = SMLoc()) argument
3644 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, unsigned ShiftImm, SMLoc S, SMLoc E) argument
5461 unsigned ShiftImm = 0; local
5806 unsigned ShiftImm = 0; local
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 2780 unsigned ShiftImm; local
2783 ShiftImm = CI->getZExtValue();
2787 if (ShiftImm == 0 || ShiftImm >=32)
2811 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 953 // This value is encoded as follows, if ShiftImm is the value within those
954 // ranges then the encoding szimm5 = ShiftImm + size, where size is either 8
957 unsigned Size, ShiftImm; local
974 ShiftImm = MI.getOperand(OpIdx).getImm();
975 return Size + ShiftImm;
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 501 unsigned ShiftImm = DefMI->getOperand(3).getImm(); local
504 unsigned NewElem = (SplatImm + ShiftImm) & 0x3;
|