Searched refs:SU (Results 1 - 25 of 64) sorted by relevance

123

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.h72 inline unsigned getNumDecoderSlots(SUnit *SU) const;
75 bool fitsIntoCurrentGroup(SUnit *SU) const;
82 /// representing the current decoder slot of the current cycle. If an SU
85 unsigned getCurrCycleIdx(SUnit *SU = nullptr) const;
104 bool isFPdOpPreferred_distance(SUnit *SU) const;
118 void EmitInstruction(SUnit *SU) override;
121 const MCSchedClassDesc *getSchedClass(SUnit *SU) const {
122 if (!SU->SchedClass && SchedModel->hasInstrSchedModel())
123 SU->SchedClass = SchedModel->resolveSchedClass(SU
[all...]
H A DSystemZHazardRecognizer.cpp46 getNumDecoderSlots(SUnit *SU) const {
47 const MCSchedClassDesc *SC = getSchedClass(SU);
61 unsigned SystemZHazardRecognizer::getCurrCycleIdx(SUnit *SU) const {
66 if (SU != nullptr && !fitsIntoCurrentGroup(SU)) {
92 SystemZHazardRecognizer::fitsIntoCurrentGroup(SUnit *SU) const {
93 const MCSchedClassDesc *SC = getSchedClass(SU);
105 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr()))
109 // SU should fit into current group. NumSlots should be 1 or 0,
111 assert ((getNumDecoderSlots(SU) <
167 dumpSU(SUnit *SU, raw_ostream &OS) const argument
271 EmitInstruction(SUnit *SU) argument
387 resourcesCost(SUnit *SU) argument
[all...]
H A DSystemZMachineScheduler.cpp29 for (auto &SU : *this) {
30 HazardRec.dumpSU(SU, dbgs());
31 if (SU != *rbegin())
176 for (auto *SU : Available) {
178 // SU is the next candidate to be compared against current Best.
179 Candidate c(SU, *HazardRec);
181 // Remeber which SU is the best candidate.
182 if (Best.SU == nullptr || c < Best) {
187 LLVM_DEBUG(HazardRec->dumpSU(c.SU, dbgs()); c.dumpCosts();
188 dbgs() << " Height:" << c.SU
241 schedNode(SUnit *SU, bool IsTopNode) argument
251 releaseTopNode(SUnit *SU) argument
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DResourcePriorityQueue.h83 void addNode(const SUnit *SU) override {
87 void updateNode(const SUnit *SU) override {}
103 /// Single cost function reflecting benefit of scheduling SU
105 int SUSchedulingCost (SUnit *SU);
109 void initNumRegDefsLeft(SUnit *SU);
110 void updateNumRegDefsLeft(SUnit *SU);
111 int regPressureDelta(SUnit *SU, bool RawPressure = false);
112 int rawRegPressureDelta (SUnit *SU, unsigned RCId);
120 void remove(SUnit *SU) override;
123 void scheduledNode(SUnit *SU) overrid
[all...]
H A DLatencyPriorityQueue.h57 void addNode(const SUnit *SU) override {
61 void updateNode(const SUnit *SU) override {
84 void remove(SUnit *SU) override;
94 void scheduledNode(SUnit *SU) override;
97 void AdjustPriorityOfUnscheduledPreds(SUnit *SU);
98 SUnit *getSingleUnscheduledPred(SUnit *SU);
H A DScheduleDAGInstrs.h55 SUnit *SU; member in struct:llvm::VReg2SUnit
57 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU) argument
58 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
70 unsigned OperandIndex, SUnit *SU)
71 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {}
77 SUnit *SU; member in struct:llvm::PhysRegSUOper
81 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
180 /// No other SU ever gets scheduled around it (except in the special
198 /// every Nth memory SU int
69 VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask, unsigned OperandIndex, SUnit *SU) argument
210 addChainDependencies(SUnit *SU, SUList &SUs, unsigned Latency) argument
[all...]
H A DMachineScheduler.h247 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
251 virtual void releaseTopNode(SUnit *SU) = 0;
255 virtual void releaseBottomNode(SUnit *SU) = 0;
359 void updateQueues(SUnit *SU, bool IsTopNode);
373 void releaseSucc(SUnit *SU, SDep *SuccEdge);
374 void releaseSuccessors(SUnit *SU);
375 void releasePred(SUnit *SU, SDep *PredEdge);
376 void releasePredecessors(SUnit *SU);
395 // Map each SU to its summary of pressure changes. This array is updated for
453 PressureDiff &getPressureDiff(const SUnit *SU) { argument
556 find(SUnit *SU) argument
558 push(SUnit *SU) argument
850 SUnit *SU; member in struct:llvm::GenericSchedulerBase::SchedCandidate
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNMinRegStrategy.cpp31 const SUnit *SU; member in struct:__anon4988::GCNMinRegScheduler::Candidate
35 : SU(SU_), Priority(Priority_) {}
44 bool isScheduled(const SUnit *SU) const {
45 assert(!SU->isBoundaryNode());
46 return NumPreds[SU->NodeNum] == std::numeric_limits<unsigned>::max();
49 void setIsScheduled(const SUnit *SU) { argument
50 assert(!SU->isBoundaryNode());
51 NumPreds[SU->NodeNum] = std::numeric_limits<unsigned>::max();
54 unsigned getNumPreds(const SUnit *SU) const {
55 assert(!SU
60 decNumPreds(const SUnit *SU) argument
199 auto SU = Worklist.pop_back_val(); local
220 releaseSuccessors(const SUnit* SU, int Priority) argument
259 auto SU = C->SU; local
[all...]
H A DGCNILPSched.cpp24 SUnit *SU; member in struct:__anon4986::GCNILPScheduler::Candidate
27 : SU(SU_) {}
41 unsigned getNodePriority(const SUnit *SU) const;
48 void releasePredecessors(const SUnit* SU);
59 CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) { argument
60 unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum];
65 for (const SDep &Pred : SU->Preds) {
87 unsigned GCNILPScheduler::getNodePriority(const SUnit *SU) const {
88 assert(SU->NodeNum < SUNumbers.size());
89 if (SU
107 closestSucc(const SUnit *SU) argument
122 calcMaxScratches(const SUnit *SU) argument
276 releasePredecessors(const SUnit* SU) argument
337 auto SU = C->SU; local
[all...]
H A DR600MachineScheduler.cpp58 SUnit *SU = nullptr; local
98 if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) ||
101 SU = pickAlu();
102 if (!SU && !PhysicalRegCopy.empty()) {
103 SU = PhysicalRegCopy.front();
106 if (SU) {
113 if (!SU) {
115 SU = pickOther(IDFetch);
116 if (SU)
121 if (!SU) {
142 schedNode(SUnit *SU, bool IsTopNode) argument
189 releaseTopNode(SUnit *SU) argument
193 releaseBottomNode(SUnit *SU) argument
293 getInstKind(SUnit* SU) argument
322 SUnit *SU = *It; local
431 SUnit *SU = AttemptFillSlot(3, true); local
440 SUnit *SU = AttemptFillSlot(Chan, false); local
454 SUnit *SU = nullptr; local
[all...]
H A DSIMachineScheduler.cpp197 void SIScheduleBlock::addUnit(SUnit *SU) { argument
198 NodeNum2Index[SU->NodeNum] = SUnits.size();
199 SUnits.push_back(SU);
205 dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason);
257 if (TryCand.SU->NodeNum < Cand.SU->NodeNum) {
265 for (SUnit* SU : TopReadySUs) {
270 TryCand.SU = SU;
299 SUnit *SU = TopReadySUs[0]; local
417 SUnit *SU = pickNode(); local
453 undoReleaseSucc(SUnit *SU, SDep *SuccEdge) argument
463 releaseSucc(SUnit *SU, SDep *SuccEdge) argument
483 releaseSuccessors(SUnit *SU, bool InOrOutBlock) argument
499 nodeScheduled(SUnit *SU) argument
644 isSUInBlock(SUnit *SU, unsigned ID) argument
654 SUnit *SU = &DAG->SUnits[i]; local
662 hasDataDependencyPred(const SUnit &SU, const SUnit &FromSU) argument
680 SUnit *SU = &DAG->SUnits[i]; local
696 const SUnit &SU = DAG->SUnits[SUNum]; local
809 SUnit *SU = &DAG->SUnits[SUNum]; local
851 SUnit *SU = &DAG->SUnits[SUNum]; local
897 SUnit *SU = &DAG->SUnits[i]; local
934 SUnit *SU = &DAG->SUnits[SUNum]; local
978 SUnit *SU = &DAG->SUnits[i]; local
1004 SUnit *SU = &DAG->SUnits[SUNum]; local
1030 SUnit *SU = &DAG->SUnits[SUNum]; local
1051 SUnit *SU = &DAG->SUnits[SUNum]; local
1073 SUnit *SU = &DAG->SUnits[SUNum]; local
1079 SUnit *SU = &DAG->SUnits[SUNum]; local
1112 SUnit *SU = &DAG->SUnits[SUNum]; local
1144 const SUnit &SU = DAG->SUnits[SUNum]; local
1219 SUnit *SU = &DAG->SUnits[i]; local
1233 SUnit *SU = &DAG->SUnits[i]; local
1828 SUnit *SU = &SUnits[ScheduledSUnits[i]]; local
1950 SUnit *SU = &SUnits[i]; local
2025 SUnit *SU = &SUnits[*I]; local
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.cpp92 /// Check if scheduling of this SU is possible
97 bool VLIWResourceModel::isResourceAvailable(SUnit *SU, bool IsTop) { argument
98 if (!SU || !SU->getInstr())
103 switch (SU->getInstr()->getOpcode()) {
105 if (!ResourcesModel->canReserveResources(*SU->getInstr()))
119 MachineBasicBlock *MBB = SU->getInstr()->getParent();
127 if (hasDependence(Packet[i], SU, QII))
131 if (hasDependence(SU, Packet[i], QII))
138 bool VLIWResourceModel::reserveResources(SUnit *SU, boo argument
228 SUnit *SU = SchedImpl->pickNode(IsTopNode); local
288 releaseTopNode(SUnit *SU) argument
304 releaseBottomNode(SUnit *SU) argument
336 checkHazard(SUnit *SU) argument
347 releaseNode(SUnit *SU, unsigned ReadyCycle) argument
389 bumpNode(SUnit *SU) argument
427 SUnit *SU = *(Pending.begin()+i); local
447 removeReady(SUnit *SU) argument
484 traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU, int Cost, PressureChange P) argument
521 isSingleUnscheduledPred(SUnit *SU, SUnit *SU2) argument
536 isSingleUnscheduledSucc(SUnit *SU, SUnit *SU2) argument
553 pressureChange(const SUnit *SU, bool isBotUp) argument
576 SchedulingCost(ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose) argument
951 SUnit *SU; local
994 schedNode(SUnit *SU, bool IsTopNode) argument
[all...]
H A DHexagonMachineScheduler.h81 bool isResourceAvailable(SUnit *SU, bool IsTop);
82 bool reserveResources(SUnit *SU, bool IsTop);
84 bool isInPacket(SUnit *SU) const { return is_contained(Packet, SU); }
115 SUnit *SU = nullptr; member in struct:llvm::ConvergingVLIWScheduler::SchedCandidate
185 for (auto &SU : DAG->SUnits)
186 MaxPath = std::max(MaxPath, isTop() ? SU.getHeight() : SU.getDepth());
195 bool checkHazard(SUnit *SU);
197 void releaseNode(SUnit *SU, unsigne
209 isLatencyBound(SUnit *SU) argument
[all...]
H A DHexagonHazardRecognizer.cpp39 HexagonHazardRecognizer::getHazardType(SUnit *SU, int stalls) { argument
40 MachineInstr *MI = SU->getInstr();
68 if (SU == UsesDotCur && DotCurPNum != (int)PacketNum) {
100 bool HexagonHazardRecognizer::ShouldPreferAnother(SUnit *SU) { argument
101 if (PrefVectorStoreNew != nullptr && PrefVectorStoreNew != SU)
103 if (UsesLoad && SU->isInstr() && SU->getInstr()->mayLoad())
105 return UsesDotCur && ((SU == UsesDotCur) ^ (DotCurPNum == (int)PacketNum));
108 void HexagonHazardRecognizer::EmitInstruction(SUnit *SU) { argument
109 MachineInstr *MI = SU
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp67 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { argument
69 for (SDep &Pred : SU->Preds) {
104 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU, argument
107 for (const SDep &Succ : SU->Succs) {
142 static unsigned numberCtrlDepsInSU(SUnit *SU) { argument
144 for (const SDep &Succ : SU->Succs)
151 static unsigned numberCtrlPredInSU(SUnit *SU) { argument
153 for (SDep &Pred : SU->Preds)
168 SUnit *SU = &(*SUnits)[i]; local
169 initNumRegDefsLeft(SU);
210 getSingleUnscheduledPred(SUnit *SU) argument
225 push(SUnit *SU) argument
239 isResourceAvailable(SUnit *SU) argument
282 reserveResources(SUnit *SU) argument
319 rawRegPressureDelta(SUnit *SU, unsigned RCId) argument
353 regPressureDelta(SUnit *SU, bool RawPressure) argument
389 SUSchedulingCost(SUnit *SU) argument
460 scheduledNode(SUnit *SU) argument
534 initNumRegDefsLeft(SUnit *SU) argument
567 adjustPriorityOfUnscheduledPreds(SUnit *SU) argument
618 remove(SUnit *SU) argument
[all...]
H A DScheduleDAGRRList.cpp211 /// IsReachable - Checks if SU is reachable from TargetSU.
212 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { argument
213 return Topo.IsReachable(SU, TargetSU);
216 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
218 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { argument
219 return Topo.WillCreateCycle(SU, TargetSU);
222 /// AddPredQueued - Queues and update to add a predecessor edge to SUnit SU.
225 void AddPredQueued(SUnit *SU, const SDep &D) { argument
226 Topo.AddPredQueued(SU, D.getSUnit());
227 SU
233 AddPred(SUnit *SU, const SDep &D) argument
241 RemovePred(SUnit *SU, const SDep &D) argument
247 isReady(SUnit *SU) argument
398 ReleasePred(SUnit *SU, const SDep *PredEdge) argument
554 ReleasePredecessors(SUnit *SU) argument
651 AdvancePastStalls(SUnit *SU) argument
693 EmitNode(SUnit *SU) argument
736 ScheduleNodeBottomUp(SUnit *SU) argument
835 UnscheduleNodeBottomUp(SUnit *SU) argument
938 SUnit *SU = *I; local
948 BacktrackBottomUp(SUnit *SU, SUnit *BtSU) argument
970 isOperandOf(const SUnit *SU, SDNode *N) argument
980 TryUnfoldSU(SUnit *SU) argument
1134 CopyAndMoveSuccessors(SUnit *SU) argument
1222 InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, SmallVectorImpl<SUnit*> &Copies) argument
1297 CheckForLiveRegDef(SUnit *SU, unsigned Reg, SUnit **LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVectorImpl<unsigned> &LRegs, const TargetRegisterInfo *TRI) argument
1319 CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask, ArrayRef<SUnit*> LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVectorImpl<unsigned> &LRegs) argument
1346 DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) argument
1437 SUnit *SU = Interferences[i-1]; local
1618 SUnit *SU = PickNodeToScheduleBottomUp(); local
1906 SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG); variable
[all...]
H A DScheduleDAGVLIW.cpp85 void releaseSucc(SUnit *SU, const SDep &D);
86 void releaseSuccessors(SUnit *SU);
87 void scheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
113 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) { argument
128 SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency());
137 void ScheduleDAGVLIW::releaseSuccessors(SUnit *SU) { argument
139 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
144 releaseSucc(SU, *I);
151 void ScheduleDAGVLIW::scheduleNodeTopDown(SUnit *SU, unsigne argument
[all...]
H A DScheduleDAGSDNodes.cpp78 SUnit *SU = &SUnits.back(); local
83 SU->SchedulingPref = Sched::None;
85 SU->SchedulingPref = TLI.getSchedulingPreference(N);
86 return SU;
90 SUnit *SU = newSUnit(Old->getNode()); local
91 SU->OrigNode = Old->OrigNode;
92 SU->Latency = Old->Latency;
93 SU->isVRegCycle = Old->isVRegCycle;
94 SU->isCall = Old->isCall;
95 SU
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.h30 bool isLoadAfterStore(SUnit *SU);
31 bool isBCTRAfterSet(SUnit *SU);
39 HazardType getHazardType(SUnit *SU, int Stalls) override;
40 bool ShouldPreferAnother(SUnit* SU) override;
41 unsigned PreEmitNoops(SUnit *SU) override;
42 void EmitInstruction(SUnit *SU) override;
78 HazardType getHazardType(SUnit *SU, int Stalls) override;
79 void EmitInstruction(SUnit *SU) override;
H A DPPCHazardRecognizers.cpp24 bool PPCDispatchGroupSBHazardRecognizer::isLoadAfterStore(SUnit *SU) { argument
26 if (isBCTRAfterSet(SU))
29 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
36 // SU is a load; for any predecessors in this dispatch group, that are stores,
38 for (unsigned i = 0, ie = (unsigned) SU->Preds.size(); i != ie; ++i) {
39 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit());
43 if (!SU->Preds[i].isNormalMemory() && !SU->Preds[i].isBarrier())
47 if (SU->Preds[i].getSUnit() == CurGroup[j])
54 bool PPCDispatchGroupSBHazardRecognizer::isBCTRAfterSet(SUnit *SU) { argument
139 getHazardType(SUnit *SU, int Stalls) argument
146 ShouldPreferAnother(SUnit *SU) argument
155 PreEmitNoops(SUnit *SU) argument
174 EmitInstruction(SUnit *SU) argument
325 getHazardType(SUnit *SU, int Stalls) argument
385 EmitInstruction(SUnit *SU) argument
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DLatencyPriorityQueue.cpp55 /// of SU, return it, otherwise return null.
56 SUnit *LatencyPriorityQueue::getSingleUnscheduledPred(SUnit *SU) { argument
58 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
73 void LatencyPriorityQueue::push(SUnit *SU) { argument
77 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
79 if (getSingleUnscheduledPred(I->getSUnit()) == SU)
82 NumNodesSolelyBlocking[SU->NodeNum] = NumNodesBlocking;
84 Queue.push_back(SU);
92 scheduledNode(SUnit *SU) argument
105 AdjustPriorityOfUnscheduledPreds(SUnit *SU) argument
134 remove(SUnit *SU) argument
[all...]
H A DScheduleDAGInstrs.cpp102 dbgs() << "SU(" << su->NodeNum << ")";
227 /// MO is an operand of SU's instruction that defines a physical register. Adds
228 /// data dependencies from SU to any uses of the physical register.
229 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { argument
230 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
238 const MCInstrDesc *DefMIDesc = &SU->getInstr()->getDesc();
246 SUnit *UseSU = I->SU;
247 if (UseSU == SU)
256 Dep = SDep(SU, SDep::Artificial);
260 SU
289 addPhysRegDeps(SUnit *SU, unsigned OperIdx) argument
393 addVRegDefDeps(SUnit *SU, unsigned OperIdx) argument
513 addVRegUseDeps(SUnit *SU, unsigned OperIdx) argument
574 SUnit *SU = newSUnit(&MI); local
628 insert(SUnit *SU, ValueType V) argument
666 addChainDependencies(SUnit *SU, Value2SUsMap &Val2SUsMap) argument
673 addChainDependencies(SUnit *SU, Value2SUsMap &Val2SUsMap, ValueType V) argument
813 SUnit *SU = MISUnitMap[&MI]; local
1258 visitPreorder(const SUnit *SU) argument
1266 visitPostorderNode(const SUnit *SU) argument
1415 follow(const SUnit *SU) argument
1436 hasDataSucc(const SUnit *SU) argument
[all...]
H A DScheduleDAG.cpp222 SUnit *SU = WorkList.pop_back_val();
223 SU->isDepthCurrent = false;
224 for (SDep &SuccDep : SU->Succs) {
237 SUnit *SU = WorkList.pop_back_val();
238 SU->isHeightCurrent = false;
239 for (SDep &PredDep : SU->Preds) {
354 LLVM_DUMP_METHOD void ScheduleDAG::dumpNodeName(const SUnit &SU) const {
355 if (&SU == &EntrySU)
357 else if (&SU == &ExitSU)
360 dbgs() << "SU(" << S
[all...]
H A DMachineScheduler.cpp601 for (const SUnit *SU : Queue)
602 dbgs() << SU->NodeNum << " ";
620 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) { argument
637 // SU->TopReadyCycle was set to CurrCycle when it was scheduled. However,
639 if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency())
640 SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency();
647 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
648 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) { argument
649 for (SDep &Succ : SU->Succs)
650 releaseSucc(SU,
657 releasePred(SUnit *SU, SDep *PredEdge) argument
685 releasePredecessors(SUnit *SU) argument
775 SUnit *SU = SchedImpl->pickNode(IsTopNode); local
878 updateQueues(SUnit *SU, bool IsTopNode) argument
931 collectVRegUses(SUnit &SU) argument
1070 updateScheduledPressure(const SUnit *SU, const std::vector<unsigned> &NewMaxPressure) argument
1115 SUnit &SU = *V2SU.SU; local
1147 SUnit *SU = V2SU.SU; local
1223 SUnit *SU = SchedImpl->pickNode(IsTopNode); local
1344 SUnit *SU = V2SU.SU; local
1389 scheduleMI(SUnit *SU, bool IsTopNode) argument
1473 SUnit *SU; member in struct:__anon4594::BaseMemOpClusterMutation::MemOpInfo
1932 getLatencyStallCycles(SUnit *SU) argument
1992 checkHazard(SUnit *SU) argument
2086 releaseNode(SUnit *SU, unsigned ReadyCycle, bool InPQueue, unsigned Idx) argument
2205 bumpNode(SUnit *SU) argument
2357 SUnit *SU = *(Pending.begin() + I); local
2376 removeReady(SUnit *SU) argument
2902 getWeakLeft(const SUnit *SU, bool isTop) argument
2913 biasPhysReg(const SUnit *SU, bool isTop) argument
2950 initCandidate(SchedCandidate &Cand, SUnit *SU, bool AtTop, const RegPressureTracker &RPTracker, RegPressureTracker &TempTracker) argument
3216 SUnit *SU; local
3255 reschedulePhysReg(SUnit *SU, bool isTop) argument
3286 schedNode(SUnit *SU, bool IsTopNode) argument
3422 SUnit *SU; local
3450 schedNode(SUnit *SU, bool IsTopNode) argument
3530 SUnit *SU = ReadyQ.back(); variable
3625 SUnit *SU; variable
3713 getNodeLabel(const SUnit *SU, const ScheduleDAG *G) argument
3725 getNodeDescription(const SUnit *SU, const ScheduleDAG *G) argument
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp34 ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { argument
37 MachineInstr *MI = SU->getInstr();
72 return ScoreboardHazardRecognizer::getHazardType(SU, Stalls);
81 void ARMHazardRecognizer::EmitInstruction(SUnit *SU) { argument
82 MachineInstr *MI = SU->getInstr();
88 ScoreboardHazardRecognizer::EmitInstruction(SU);

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