| /freebsd-12-stable/crypto/openssl/crypto/sha/asm/ |
| H A D | sha512-ppc.pl | 84 $ROR="rotrdi";
96 $ROR="rotrwi";
134 $ROR $a0,$e,$Sigma1[0]
135 $ROR $a1,$e,$Sigma1[1]
140 $ROR $a1,$a1,`$Sigma1[2]-$Sigma1[1]`
147 $ROR $a0,$a,$Sigma0[0]
148 $ROR $a1,$a,$Sigma0[1]
152 $ROR $a1,$a1,`$Sigma0[2]-$Sigma0[1]`
173 $ROR $a0,@X[($i+1)%16],$sigma0[0]
174 $ROR
[all...] |
| H A D | sha1-thumb.pl | 57 add $t2,$e @ E+=ROR(A,27)
67 orr $c,$b @ C=ROR(B,2)
|
| /freebsd-12-stable/secure/lib/libcrypto/arm/ |
| H A D | sha1-armv4-large.S | 51 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
57 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
76 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
82 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
101 add r5,r5,r6,ror#27 @ E+=ROR(A,27)
107 add r5,r5,r6,ror#27 @ E+=ROR(A,27)
126 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
132 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
151 add r3,r3,r4,ror#27 @ E+=ROR(A,27)
157 add r3,r3,r4,ror#27 @ E+=ROR(
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 37 ROR, enumerator in enum:llvm::AArch64_AM::ShiftExtendType
58 case AArch64_AM::ROR: return "ror";
79 case 3: return AArch64_AM::ROR;
107 case AArch64_AM::ROR: STEnc = 3; break;
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.h | 41 ROR, ///< Bit rotate right. enumerator in enum:llvm::AVRISD::NodeType
|
| H A D | AVRISelLowering.cpp | 258 NODE(ROR);
320 Opc8 = AVRISD::ROR;
|
| /freebsd-12-stable/contrib/llvm-project/lldb/source/Plugins/Process/Utility/ |
| H A D | ARMUtils.h | 181 static inline uint32_t ROR(const uint32_t value, const uint32_t amount, function in namespace:lldb_private
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 455 ROR, enumerator in enum:llvm::AArch64SE::ShiftExtSpecifiers
|
| /freebsd-12-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/ |
| H A D | EmulateInstructionARM.cpp | 1764 R[t] = ROR(data, 8*UInt(address<1:0>));
3773 // A8.6.139 ROR (immediate) -- Encoding T1
3816 // A8.6.139 ROR (immediate)
6369 R[t] = ROR(data, 8*UInt(address<1:0>));
6474 // R[t] = ROR(data, 8*UInt(address<1:0>));
6475 data = ROR(data, Bits32(address, 1, 0), &success);
6508 R[t] = ROR(data, 8*UInt(address<1:0>));
6680 // R[t] = ROR(data, 8*UInt(address<1:0>));
6681 data = ROR(data, Bits32(address, 1, 0), &success);
8358 rotated = ROR(
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1209 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR ||
1312 // A logical shifter is LSL, LSR, ASR or ROR.
1315 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR) &&
2748 .Case("ror", AArch64_AM::ROR)
2770 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR ||
|
| /freebsd-12-stable/sys/dev/axgbe/ |
| H A D | xgbe-dev.c | 1906 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1);
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 406 return AArch64_AM::ROR;
461 /// instructions do not. The AllowROR parameter specifies whether ROR is
468 if (!AllowROR && ShType == AArch64_AM::ROR)
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 2553 case Mips::ROR:
4771 if (Inst.getOpcode() == Mips::ROR) {
4787 case Mips::ROR:
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 5920 if (SDValue ROR = reassociateOps(ISD::OR, SDLoc(N), N0, N1, N->getFlags()))
5921 return ROR;
|