/freebsd-12-stable/sys/arm/freescale/imx/ |
H A D | imx6_ccm.c | 68 RD4(struct ccm_softc *sc, bus_size_t off) function 179 reg = RD4(sc, CCM_CGPR); 182 reg = RD4(sc, CCM_CLPCR); 226 reg = RD4(sc, CCM_CSCMR1); 241 reg = RD4(sc, CCM_CS1CDR); 255 reg = RD4(sc, CCM_CS2CDR); 273 WR4(ccm_sc, CCM_CCGR6, RD4(ccm_sc, CCM_CCGR6) | CCGR_CLK_MODE_ALWAYS); 327 WR4(ccm_sc, CCM_CCGR5, RD4(ccm_sc, CCM_CCGR5) | CCGR5_SATA); 330 v = RD4(ccm_sc, CCM_ANALOG_PLL_ENET); 335 if (RD4(ccm_s [all...] |
H A D | imx6_snvs.c | 82 RD4(struct snvs_softc *sc, bus_size_t offset) function 108 while ((RD4(sc, SNVS_LPCR) & LPCR_SRTC_ENV) != enbit) 121 if (!(RD4(sc, SNVS_LPCR) & LPCR_SRTC_ENV)) { 133 counter1 = (uint64_t)RD4(sc, SNVS_LPSRTCMR) << (SBT_LSB + 32); 134 counter1 |= (uint64_t)RD4(sc, SNVS_LPSRTCLR) << (SBT_LSB); 135 counter2 = (uint64_t)RD4(sc, SNVS_LPSRTCMR) << (SBT_LSB + 32); 136 counter2 |= (uint64_t)RD4(sc, SNVS_LPSRTCLR) << (SBT_LSB);
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H A D | imx6_src.c | 59 RD4(struct src_softc *sc, bus_size_t off) function 81 reg = RD4(src_sc, SRC_SCR); 86 reg = RD4(src_sc, SRC_SCR);
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/freebsd-12-stable/sys/arm/broadcom/bcm2835/ |
H A D | bcm2835_sdhost.c | 238 RD4(struct bcm_sdhost_softc *sc, bus_size_t off) function 260 val = RD4(sc, off & ~3); 271 val = RD4(sc, off & ~3); 281 val32 = RD4(sc, off & ~3); 292 val32 = RD4(sc, off & ~3); 308 RD4(sc, HC_COMMAND)); 310 RD4(sc, HC_ARGUMENT)); 312 RD4(sc, HC_TIMEOUTCOUNTER)); 314 RD4(sc, HC_CLOCKDIVISOR)); 316 RD4(s [all...] |
/freebsd-12-stable/sys/arm/nvidia/tegra124/ |
H A D | tegra124_clk_pll.c | 419 RD4(sc, sc->base_reg, ®); 432 RD4(sc, sc->base_reg, ®); 497 RD4(sc, sc->base_reg, &val); 523 RD4(sc, sc->misc_reg, ®); 528 RD4(sc, sc->misc_reg, ®); 533 RD4(sc, sc->base_reg, ®); 572 RD4(sc, sc->base_reg, ®); 576 RD4(sc, PLLE_AUX, ®); 582 RD4(sc, sc->misc_reg, ®); 592 RD4(s [all...] |
H A D | tegra124_pmc.c | 136 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) macro 191 reg = RD4(sc, PMC_PWRGATE_STATUS) & PMC_PWRGATE_STATUS_PARTID(id); 198 reg = RD4(sc, PMC_PWRGATE_TOGGLE); 211 reg = RD4(sc, PMC_PWRGATE_TOGGLE); 238 reg = RD4(sc, PMC_PWRGATE_STATUS); 251 reg = RD4(sc, PMC_REMOVE_CLAMPING_CMD); 259 reg = RD4(sc, PMC_CLAMP_STATUS); 274 reg = RD4(sc, PMC_PWRGATE_STATUS); 513 reg = RD4(sc, PMC_CNTRL); 518 reg = RD4(s [all...] |
H A D | tegra124_xusbpadctl.c | 178 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) macro 376 reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP); 385 reg = RD4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx)); 397 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 402 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 407 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 421 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 426 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2); 433 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 439 reg = RD4(s [all...] |
H A D | tegra124_clk_super.c | 163 RD4(sc, sc->base_reg, ®); 201 RD4(sc, sc->base_reg, ®); 215 RD4(sc, sc->base_reg, &dummy); 219 RD4(sc, sc->base_reg, &dummy); 226 RD4(sc, sc->base_reg, &dummy);
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/freebsd-12-stable/sys/dev/cadence/ |
H A D | if_cgem.c | 202 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) macro 236 uint32_t low = RD4(sc, CGEM_SPEC_ADDR_LOW(i)); 237 uint32_t high = RD4(sc, CGEM_SPEC_ADDR_HI(i)) & 0xffff; 318 net_cfg = RD4(sc, CGEM_NET_CFG); 842 sc->stats.tx_bytes += RD4(sc, CGEM_OCTETS_TX_BOT); 843 sc->stats.tx_bytes += (uint64_t)RD4(sc, CGEM_OCTETS_TX_TOP) << 32; 845 sc->stats.tx_frames += RD4(sc, CGEM_FRAMES_TX); 846 sc->stats.tx_frames_bcast += RD4(sc, CGEM_BCAST_FRAMES_TX); 847 sc->stats.tx_frames_multi += RD4(sc, CGEM_MULTI_FRAMES_TX); 848 sc->stats.tx_frames_pause += RD4(s [all...] |
/freebsd-12-stable/sys/arm/xilinx/ |
H A D | zy7_slcr.c | 78 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) macro 141 RD4(sc, ZY7_SLCR_REBOOT_STAT) & 0xf0ffffff); 275 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); 301 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); 365 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); 414 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); 494 reg = RD4(sc, ZY7_SLCR_FPGA_THR_CNT(unit)); 511 reg = RD4(sc, ZY7_SLCR_LVL_SHFTR_EN); 600 bootmode = RD4(sc, ZY7_SLCR_BOOT_MODE); 605 pss_idcode = RD4(s [all...] |
H A D | zy7_gpio.c | 99 #define RD4(sc, off) bus_read_4((sc)->mem_res, (off)) macro 180 if ((RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & (1 << (pin & 31))) != 0) { 182 if ((RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & (1 << (pin & 31))) == 0) 209 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) | (1 << (pin & 31))); 213 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & 217 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) | 222 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & ~(1 << (pin & 31))); 224 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & ~(1 << (pin & 31))); 263 *value = (RD4(sc, ZY7_GPIO_DATA_RO(pin >> 5)) >> (pin & 31)) & 1; 280 RD4(s [all...] |
H A D | uart_dev_cdnc.c | 59 #define RD4(bas, reg) \ macro 339 while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) & 345 while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) & 357 return ((RD4(bas, CDNC_UART_CHAN_STAT_REG) & 371 while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) & 378 c = RD4(bas, CDNC_UART_FIFO); 499 modem_ctrl = RD4(bas, CDNC_UART_MODEM_CTRL_REG) & 521 status = RD4(bas, CDNC_UART_ISTAT_REG); 531 while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) & 533 c = RD4(ba [all...] |
/freebsd-12-stable/sys/dev/sdhci/ |
H A D | fsl_sdhci.c | 192 RD4(struct fsl_sdhci_softc *sc, bus_size_t off) function 217 wrk32 = RD4(sc, SDHC_PROT_CTRL); 257 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); 279 return (RD4(sc, USDHC_MIX_CONTROL) & 0x37); 302 val32 = RD4(sc, SDHCI_INT_STATUS); 303 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE); 315 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); 324 val32 = RD4(sc, off); 392 val32 = RD4(sc, SDHC_PROT_CTRL); 416 val32 = RD4(s [all...] |
/freebsd-12-stable/sys/dev/tpm/ |
H A D | tpm_crb.c | 191 crb_sc->rsp_off = RD4(sc, TPM_CRB_CTRL_RSP_ADDR); 192 crb_sc->rsp_off |= ((uint64_t) RD4(sc, TPM_CRB_CTRL_RSP_HADDR) << 32); 194 crb_sc->cmd_off = RD4(sc, TPM_CRB_CTRL_CMD_LADDR); 195 crb_sc->cmd_off |= ((uint64_t) RD4(sc, TPM_CRB_CTRL_CMD_HADDR) << 32); 196 crb_sc->cmd_buf_size = RD4(sc, TPM_CRB_CTRL_CMD_SIZE); 197 crb_sc->rsp_buf_size = RD4(sc, TPM_CRB_CTRL_RSP_SIZE); 252 if ((RD4(sc, off) & mask) == val) 256 if ((RD4(sc, off) & mask) == val) 324 if (RD4(sc, TPM_CRB_CTRL_STS) & TPM_CRB_CTRL_STS_ERR_BIT) { 338 if (!(RD4(s [all...] |
H A D | tpm20.h | 148 RD4(struct tpm_sc *sc, bus_size_t off) function 177 WR4(sc, off, RD4(sc, off) & val); 189 WR4(sc, off, RD4(sc, off) | val);
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/freebsd-12-stable/sys/arm/nvidia/ |
H A D | tegra_efuse.c | 53 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_sc)->fuse_begin + (_r)) macro 189 sku->sku_id = RD4(sc, TEGRA124_FUSE_SKU_INFO); 190 sku->soc_iddq_value = RD4(sc, TEGRA124_FUSE_SOC_IDDQ); 191 sku->cpu_iddq_value = RD4(sc, TEGRA124_FUSE_CPU_IDDQ); 192 sku->gpu_iddq_value = RD4(sc, TEGRA124_FUSE_GPU_IDDQ); 193 sku->soc_speedo_value = RD4(sc, TEGRA124_FUSE_SOC_SPEEDO_0); 194 sku->cpu_speedo_value = RD4(sc, TEGRA124_FUSE_CPU_SPEEDO_0); 195 sku->gpu_speedo_value = RD4(sc, TEGRA124_FUSE_CPU_SPEEDO_2); 234 return (RD4(dev_sc, addr));
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H A D | tegra_soctherm.c | 127 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) macro 374 val = RD4(sc, sensor->sensor_base + TSENSOR_CONFIG0); 393 val = RD4(sc, sensor->sensor_base + TSENSOR_CONFIG0); 399 RD4(sc, sensor->sensor_base + TSENSOR_CONFIG0), 400 RD4(sc, sensor->sensor_base + TSENSOR_CONFIG1), 401 RD4(sc, sensor->sensor_base + TSENSOR_CONFIG2), 402 RD4(sc, sensor->sensor_base + TSENSOR_STATUS0), 403 RD4(sc, sensor->sensor_base + TSENSOR_STATUS1), 404 RD4(sc, sensor->sensor_base + TSENSOR_STATUS2) 432 val = RD4(s [all...] |
H A D | tegra_usbphy.c | 312 #define RD4(sc, offs) \ macro 324 if ((RD4(sc, reg) & mask) == val) 337 val = RD4(sc, CTRL_USB_HOSTPC1_DEVLC); 360 val = RD4(sc, IF_USB_SUSP_CTRL); 365 val = RD4(sc, UTMIP_TX_CFG0); 369 val = RD4(sc, UTMIP_HSRX_CFG0); 376 val = RD4(sc, UTMIP_HSRX_CFG1); 381 val = RD4(sc, UTMIP_DEBOUNCE_CFG0); 386 val = RD4(sc, UTMIP_MISC_CFG0); 391 val = RD4(s [all...] |
H A D | tegra_rtc.c | 78 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) macro 113 if ((RD4(sc, RTC_BUSY) & RTC_BUSY_STATUS) == 0) 136 msec = RD4(sc, RTC_MILLI_SECONDS); 137 sec = RD4(sc, RTC_SHADOW_SECONDS); 172 status = RD4(sc, RTC_INTR_STATUS);
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/freebsd-12-stable/sys/dev/extres/clk/ |
H A D | clk_mux.c | 45 #define RD4(_clk, off, val) \ macro 84 rv = RD4(clk, sc->offset, ®); 110 RD4(clk, sc->offset, ®);
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H A D | clk_gate.c | 45 #define RD4(_clk, off, val) \ macro 84 rv = RD4(clk, sc->offset, ®); 110 RD4(clk, sc->offset, ®);
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/freebsd-12-stable/sys/arm64/rockchip/clk/ |
H A D | rk_clk_mux.c | 50 #define RD4(_clk, off, val) \ macro 89 rv = RD4(clk, sc->offset, ®); 115 RD4(clk, sc->offset, ®);
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H A D | rk_clk_gate.c | 44 #define RD4(_clk, off, val) \ macro 83 rv = RD4(clk, sc->offset, ®); 110 RD4(clk, sc->offset, ®);
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/freebsd-12-stable/sys/arm/mv/ |
H A D | mv_thermal.c | 126 #define RD4(sc, reg) \ macro 147 reg = RD4(sc, STATUS); 168 reg = RD4(sc, CONTROL0); 190 reg = RD4(sc, CONTROL0); 207 reg = RD4(sc, STATUS) & STATUS_TEMP_MASK; 226 reg = RD4(sc, CONTROL0); 246 reg = RD4(sc, CONTROL1); 252 reg = RD4(sc, CONTROL0);
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/freebsd-12-stable/sys/dev/ffec/ |
H A D | if_ffec.c | 225 RD4(struct ffec_softc *sc, bus_size_t off) function 311 if (RD4(sc, FEC_IER_REG) & FEC_IER_MII) 337 val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK; 388 ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED; 389 rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE | 391 tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN; 483 mibc = RD4(sc, FEC_MIBC_REG); 530 if_inc_counter(ifp, IFCOUNTER_IPACKETS, RD4(sc, FEC_RMON_R_PACKETS)); 531 if_inc_counter(ifp, IFCOUNTER_IMCASTS, RD4(sc, FEC_RMON_R_MC_PKT)); 533 RD4(s [all...] |