Searched refs:PredEdge (Results 1 - 6 of 6) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNILPSched.cpp277 for (const auto &PredEdge : SU->Preds) {
278 auto PredSU = PredEdge.getSUnit();
279 if (PredEdge.isWeak())
283 PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge.getLatency());
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp99 void ReleasePred(SUnit *SU, SDep *PredEdge);
139 void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) { argument
140 SUnit *PredSU = PredEdge->getSUnit();
H A DScheduleDAGRRList.cpp252 void ReleasePred(SUnit *SU, const SDep *PredEdge);
259 void CapturePred(SDep *PredEdge);
398 void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) { argument
399 SUnit *PredSU = PredEdge->getSUnit();
414 PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge->getLatency());
820 void ScheduleDAGRRList::CapturePred(SDep *PredEdge) { argument
821 SUnit *PredSU = PredEdge->getSUnit();
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineScheduler.h375 void releasePred(SUnit *SU, SDep *PredEdge);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineScheduler.cpp657 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) { argument
658 SUnit *PredSU = PredEdge->getSUnit();
660 if (PredEdge->isWeak()) {
662 if (PredEdge->isCluster())
676 if (PredSU->BotReadyCycle < SU->BotReadyCycle + PredEdge->getLatency())
677 PredSU->BotReadyCycle = SU->BotReadyCycle + PredEdge->getLatency();
H A DMachinePipeliner.cpp2704 for (SDep &PredEdge : SU->Preds) {
2705 SUnit *PredSU = PredEdge.getSUnit();

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