Searched refs:PhiReg (Results 1 - 4 of 4) sorted by relevance
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonHardwareLoops.cpp | 1638 Register PhiReg = Phi->getOperand(i).getReg(); local 1639 MachineInstr *DI = MRI->getVRegDef(PhiReg);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | ModuloSchedule.cpp | 1651 Register PhiReg = MI.getOperand(0).getReg(); local 1654 MI.getOperand(0).setReg(PhiReg);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPURegisterBankInfo.cpp | 764 Register PhiReg = MRI.createGenericVirtualRegister(ResTy); local 766 PhiRegs.push_back(PhiReg); 767 MRI.setRegBank(PhiReg, *DefBank);
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H A D | SIISelLowering.cpp | 3179 unsigned PhiReg, 3195 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiReg) 3280 unsigned PhiReg, 3311 InitResultReg, DstReg, PhiReg, TmpExec, 3442 Register PhiReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); local 3447 auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg, 3557 Register PhiReg = MRI.createVirtualRegister(VecRC); local 3559 auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg, 3565 .addReg(PhiReg, RegState::Undef, SubReg) // vdst 3568 .addReg(PhiReg, RegStat 3170 emitLoadM0FromVGPRLoop( const SIInstrInfo *TII, MachineRegisterInfo &MRI, MachineBasicBlock &OrigBB, MachineBasicBlock &LoopBB, const DebugLoc &DL, const MachineOperand &IdxReg, unsigned InitReg, unsigned ResultReg, unsigned PhiReg, unsigned InitSaveExecReg, int Offset, bool UseGPRIdxMode, bool IsIndirectSrc) argument 3276 loadM0FromVGPR(const SIInstrInfo *TII, MachineBasicBlock &MBB, MachineInstr &MI, unsigned InitResultReg, unsigned PhiReg, int Offset, bool UseGPRIdxMode, bool IsIndirectSrc) argument [all...] |
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