Searched refs:OpRC (Results 1 - 7 of 7) sorted by relevance
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | BreakFalseDeps.cpp | 125 const TargetRegisterClass *OpRC = local 132 !OpRC->contains(CurrMO.getReg())) 144 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC);
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H A D | MachineInstr.cpp | 902 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); local 908 if (OpRC) 909 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx); 912 } else if (OpRC) 913 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 312 const TargetRegisterClass *OpRC = nullptr; 314 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF); 316 if (OpRC) { 318 = MRI->constrainRegClass(VReg, OpRC, MinRCSize); 320 OpRC = TRI->getAllocatableClass(OpRC); 321 assert(OpRC && "Constraints cannot be fulfilled for allocation"); 322 Register NewVReg = MRI->createVirtualRegister(OpRC); 381 const TargetRegisterClass *OpRC = 388 if (OpRC [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86SpeculativeLoadHardening.cpp | 2035 auto *OpRC = MRI->getRegClass(OpReg); local 2036 Register TmpReg = MRI->createVirtualRegister(OpRC); 2040 if (!Subtarget->hasVLX() && (OpRC->hasSuperClassEq(&X86::VR128RegClass) || 2041 OpRC->hasSuperClassEq(&X86::VR256RegClass))) { 2043 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128RegClass); 2057 Register VBStateReg = MRI->createVirtualRegister(OpRC); 2077 } else if (OpRC->hasSuperClassEq(&X86::VR128XRegClass) || 2078 OpRC->hasSuperClassEq(&X86::VR256XRegClass) || 2079 OpRC->hasSuperClassEq(&X86::VR512RegClass)) { 2081 bool Is128Bit = OpRC [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIFixSGPRCopies.cpp | 794 const TargetRegisterClass *OpRC = 796 if (!TRI->isSGPRClass(OpRC) && OpRC != &AMDGPU::VS_32RegClass && 797 OpRC != &AMDGPU::VS_64RegClass) {
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H A D | SIInstrInfo.cpp | 4290 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg( 4294 if (DstRC == OpRC) 4554 const TargetRegisterClass *OpRC = 4556 if (RI.hasVectorRegisters(OpRC)) { 4557 VRC = OpRC; 4559 SRC = OpRC; 4616 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg()); 4617 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC); 4618 if (VRC == OpRC) 5823 const TargetRegisterClass *OpRC [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitSimplify.cpp | 1876 auto *OpRC = HII.getRegClass(HII.get(Opc), OpNum, &HRI, MF); 1878 return OpRC->hasSubClassEq(RRC);
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