/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600ExpandSpecialInstrs.cpp | 98 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); 105 R600::OpName::pred_sel); 107 R600::OpName::pred_sel); 127 TII->setImmOperand(*PredSet, R600::OpName::update_exec_mask, 1); 129 TII->setImmOperand(*PredSet, R600::OpName::update_pred, 1); 159 BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src0)) 162 BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src1)) 209 MI.getOperand(TII->getOperandIdx(MI, R600::OpName::dst)).getReg(); 211 MI.getOperand(TII->getOperandIdx(MI, R600::OpName::src0)).getReg(); 216 int Src1Idx = TII->getOperandIdx(MI, R600::OpName [all...] |
H A D | SIPeepholeSDWA.cpp | 334 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) { 335 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) { 338 } else if (TII->getNamedOperand(*MI, AMDGPU::OpName::src1) == SrcOp) { 339 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers)) { 369 MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::src0); 370 MachineOperand *SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src0_sel); 372 TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers); 376 Src = TII->getNamedOperand(MI, AMDGPU::OpName::src1); 377 SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src1_sel); 378 SrcMods = TII->getNamedOperand(MI, AMDGPU::OpName [all...] |
H A D | R600InstrInfo.cpp | 90 NewMI->getOperand(getOperandIdx(*NewMI, R600::OpName::src0)) 156 return isLDSInstr(Opcode) && getOperandIdx(Opcode, R600::OpName::dst) != -1; 256 {R600::OpName::src0, R600::OpName::src0_sel}, 257 {R600::OpName::src1, R600::OpName::src1_sel}, 258 {R600::OpName::src2, R600::OpName::src2_sel}, 259 {R600::OpName::src0_X, R600::OpName [all...] |
H A D | GCNDPPCombine.cpp | 174 auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst); 179 const int OldIdx = AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::old); 196 AMDGPU::OpName::src0_modifiers)) { 198 AMDGPU::OpName::src0_modifiers)); 203 AMDGPU::OpName::src0_modifiers) != -1) { 207 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); 219 AMDGPU::OpName::src1_modifiers)) { 221 AMDGPU::OpName::src1_modifiers)); 226 AMDGPU::OpName::src1_modifiers) != -1) { 230 if (auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName [all...] |
H A D | R600ClauseMergePass.cpp | 87 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT)) 94 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled)) 100 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); 119 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); 131 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE0); 133 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK0); 135 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR0); 147 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE1); 149 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK1); 151 TII->getOperandIdx(R600::CF_ALU, R600::OpName [all...] |
H A D | AMDGPUMacroFusion.cpp | 48 AMDGPU::OpName::src2);
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H A D | SIFixupVectorISel.cpp | 177 MachineOperand *Op = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); 183 bool HasVdst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst) != nullptr; 184 MachineOperand *VData = TII->getNamedOperand(MI, AMDGPU::OpName::vdata); 193 NewGlob->addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::offset)); 195 MachineOperand *Glc = TII->getNamedOperand(MI, AMDGPU::OpName::glc); 200 MachineOperand *DLC = TII->getNamedOperand(MI, AMDGPU::OpName::dlc); 204 NewGlob->addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::slc)); 207 AMDGPU::OpName::vdst_in);
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H A D | SIAddIMGInit.cpp | 79 MachineOperand *TFE = TII->getNamedOperand(MI, AMDGPU::OpName::tfe); 80 MachineOperand *LWE = TII->getNamedOperand(MI, AMDGPU::OpName::lwe); 81 MachineOperand *D16 = TII->getNamedOperand(MI, AMDGPU::OpName::d16); 99 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdata); 103 TII->getNamedOperand(MI, AMDGPU::OpName::dmask);
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H A D | SILoadStoreOptimizer.cpp | 289 TII.getNamedOperand(MI, AMDGPU::OpName::dmask)->getImm(); 330 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr) == -1) 497 DMask = TII.getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm(); 499 int OffsetIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::offset); 504 Format = TII.getNamedOperand(*I, AMDGPU::OpName::format)->getImm(); 511 GLC = TII.getNamedOperand(*I, AMDGPU::OpName::glc)->getImm(); 513 SLC = TII.getNamedOperand(*I, AMDGPU::OpName::slc)->getImm(); 515 DLC = TII.getNamedOperand(*I, AMDGPU::OpName::dlc)->getImm(); 523 AddrOpName[NumAddresses++] = AMDGPU::OpName::addr; 527 AddrOpName[NumAddresses++] = AMDGPU::OpName [all...] |
H A D | SIFoldOperands.cpp | 149 int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2); 177 OpNo == AMDGPU::getNamedOperandIdx(UseMI.getOpcode(), AMDGPU::OpName::vaddr); 202 if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0)) 203 ModIdx = AMDGPU::OpName::src0_modifiers; 204 else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1)) 205 ModIdx = AMDGPU::OpName::src1_modifiers; 206 else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2)) 207 ModIdx = AMDGPU::OpName::src2_modifiers; 337 (int)OpNo == AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)) { 615 MachineOperand *SOff = TII->getNamedOperand(*UseMI, AMDGPU::OpName [all...] |
H A D | R600Packetizer.cpp | 86 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write); 89 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst); 131 R600::OpName::src0, 132 R600::OpName::src1, 133 R600::OpName::src2 187 int OpI = TII->getOperandIdx(MII->getOpcode(), R600::OpName::pred_sel), 188 OpJ = TII->getOperandIdx(MIJ->getOpcode(), R600::OpName::pred_sel); 222 unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), R600::OpName::last); 303 R600::OpName::bank_swizzle); 307 TII->getOperandIdx(MI.getOpcode(), R600::OpName [all...] |
H A D | SIOptimizeExecMaskingPreRA.cpp | 112 auto Op = TII.getNamedOperand(MI, AMDGPU::OpName::src1); 115 Op = TII.getNamedOperand(MI, AMDGPU::OpName::src0); 231 MachineOperand *Op1 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src0); 232 MachineOperand *Op2 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src1); 243 if (TII->hasModifiersSet(*Sel, AMDGPU::OpName::src0_modifiers) || 244 TII->hasModifiersSet(*Sel, AMDGPU::OpName::src1_modifiers)) 247 Op1 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src0); 248 Op2 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src1); 249 MachineOperand *CC = TII->getNamedOperand(*Sel, AMDGPU::OpName::src2);
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H A D | SIInstrInfo.cpp | 105 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) { argument 109 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName); 110 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName); 172 int Offset0Idx = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset); 173 int Offset1Idx = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset); 190 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::sbase) == -1 || 191 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::sbase) == -1) 217 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) || 218 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) || 219 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName [all...] |
H A D | R600ISelLowering.cpp | 304 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); 364 int Idx = TII->getOperandIdx(*MIB, R600::OpName::literal); 373 TII->setImmOperand(*NewMI, R600::OpName::src0_sel, 2092 bool HasDst = TII->getOperandIdx(Opcode, R600::OpName::dst) > -1; 2103 TII->getOperandIdx(Opcode, R600::OpName::src0), 2104 TII->getOperandIdx(Opcode, R600::OpName::src1), 2105 TII->getOperandIdx(Opcode, R600::OpName::src2), 2106 TII->getOperandIdx(Opcode, R600::OpName::src0_X), 2107 TII->getOperandIdx(Opcode, R600::OpName::src0_Y), 2108 TII->getOperandIdx(Opcode, R600::OpName [all...] |
H A D | SIRegisterInfo.cpp | 317 AMDGPU::OpName::offset); 327 AMDGPU::OpName::vaddr) && 394 MachineOperand *FIOp = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); 401 assert(TII->getNamedOperand(MI, AMDGPU::OpName::soffset)->getReg() == 405 MachineOperand *OffsetOp = TII->getNamedOperand(MI, AMDGPU::OpName::offset); 590 const MachineOperand *Reg = TII->getNamedOperand(*MI, AMDGPU::OpName::vdata); 597 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)) 598 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)) 608 AMDGPU::OpName::vdata_in); 647 hasAGPRs(RC) ? TII->getNamedOperand(*MI, AMDGPU::OpName [all...] |
H A D | R600Defines.h | 64 namespace OpName { namespace
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H A D | GCNHazardRecognizer.cpp | 111 AMDGPU::OpName::gds); 127 AMDGPU::OpName::simm16); 677 int VDataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata); 690 TII->getNamedOperand(MI, AMDGPU::OpName::soffset); 703 int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::srsrc); 710 int DataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata); 790 TII->getNamedOperand(*RWLane, AMDGPU::OpName::src1); 893 auto *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0); 957 SDSTName = AMDGPU::OpName::vdst; 960 SDSTName = AMDGPU::OpName [all...] |
H A D | SILowerSGPRSpills.cpp | 280 AMDGPU::OpName::vaddr); 283 TII->getNamedOperand(MI, AMDGPU::OpName::vdata)->getReg(); 294 int FI = TII->getNamedOperand(MI, AMDGPU::OpName::addr)->getIndex();
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
H A D | AMDGPUDisassembler.cpp | 260 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 370 AMDGPU::OpName::src2_modifiers); 375 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 377 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 400 AMDGPU::OpName::vdst_in); 411 AMDGPU::OpName::vdst_in); 425 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 427 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 429 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 433 AMDGPU::OpName [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblySetP2AlignOperands.cpp | 88 MI.getOpcode(), WebAssembly::OpName::p2align);
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H A D | WebAssemblyRegisterInfo.cpp | 74 MI.getOpcode(), WebAssembly::OpName::addr); 77 MI.getOpcode(), WebAssembly::OpName::off);
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/freebsd-12-stable/contrib/llvm-project/clang/lib/Tooling/Transformer/ |
H A D | Stencil.cpp | 118 StringRef OpName; local 121 OpName = "expression"; 124 OpName = "deref"; 127 OpName = "maybeDeref"; 130 OpName = "addressOf"; 133 OpName = "maybeAddressOf"; 136 return (OpName + "(\"" + Data.Id + "\")").str();
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/freebsd-12-stable/sys/contrib/dev/acpica/compiler/ |
H A D | asloffset.c | 170 char *OpName, 444 * OpName - Name of the AML opcode 461 char *OpName, 493 Offset, ACPI_FORMAT_UINT64 (Value), OpName); 456 LsEmitOffsetTableEntry( UINT32 FileId, ACPI_NAMESPACE_NODE *Node, UINT32 NamepathOffset, UINT32 Offset, char *OpName, UINT64 Value, UINT8 AmlOpcode, UINT16 ParentOpcode) argument
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/freebsd-12-stable/contrib/llvm-project/clang/lib/AST/ |
H A D | DeclarationName.cpp | 165 const char *OpName = getOperatorSpelling(getCXXOverloadedOperator()); local 166 assert(OpName && "not an overloaded operator"); 169 if (OpName[0] >= 'a' && OpName[0] <= 'z') 171 OS << OpName; local
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/freebsd-12-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | CodeGenInstruction.cpp | 179 std::string OpName = Op.substr(1); local 183 std::string::size_type DotIdx = OpName.find_first_of('.'); 185 SubOpName = OpName.substr(DotIdx+1); 190 OpName = OpName.substr(0, DotIdx); 193 unsigned OpIdx = getOperandNamed(OpName); 342 std::string OpName = P.first; local 344 if (OpName.empty()) break; 347 std::pair<unsigned,unsigned> Op = ParseOperandName(OpName, false);
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