Searched refs:Op5 (Results 1 - 4 of 4) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp647 unsigned Op1, Op2, Op3, Op4, Op5, Op6; local
652 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
659 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
681 unsigned Op1, Op2, Op3, Op4, Op5; local
686 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
694 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp6433 auto &Op5 = static_cast<ARMOperand &>(*Operands[5]); local
6438 (Op5.isReg() && Op5.getReg() == ARM::PC);
6441 (Op5.isReg() && Op5.getReg() == ARM::SP)) &&
6443 Op5.isImm() && !Op5.isImm0_508s4());
6462 // Op4 and Op5. The 'ADD Rdm, SP, Rdm' form is already handled specially
6464 const ARMOperand *LastOp = &Op5;
6466 if (!Transform && Op5
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h1222 SDValue Op3, SDValue Op4, SDValue Op5);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp7685 SDValue Op3, SDValue Op4, SDValue Op5) {
7686 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 };

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