| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFrameLowering.cpp | 193 Register OffsetReg = MRI.createVirtualRegister(PtrRC); local
194 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg)
199 .addReg(OffsetReg);
247 Register OffsetReg = MRI.createVirtualRegister(PtrRC); local
248 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg)
255 .addReg(OffsetReg);
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.h | 51 unsigned OffsetReg,
57 unsigned OffsetReg,
247 unsigned OffsetReg) const;
255 unsigned OffsetReg) const;
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| H A D | R600InstrInfo.cpp | 1040 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg();
1041 if (OffsetReg == R600::INDIRECT_BASE_ADDR) {
1046 OffsetReg);
1054 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg();
1055 if (OffsetReg == R600::INDIRECT_BASE_ADDR) {
1061 OffsetReg);
1116 unsigned OffsetReg) const {
1117 return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0);
1123 unsigned OffsetReg,
1134 R600::AR_X, OffsetReg);
[all...] |
| H A D | SIFrameLowering.cpp | 120 MCPhysReg OffsetReg = findScratchNonCalleeSaveRegister( local
123 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32), OffsetReg)
128 .addReg(OffsetReg, RegState::Kill)
167 MCPhysReg OffsetReg = findScratchNonCalleeSaveRegister( local
170 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32), OffsetReg)
175 .addReg(OffsetReg, RegState::Kill)
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| H A D | AMDGPUCallLowering.cpp | 356 Register OffsetReg = MRI.createGenericVirtualRegister(LLT::scalar(64)); local
357 B.buildConstant(OffsetReg, Offset);
359 B.buildPtrAdd(DstReg, KernArgSegmentVReg, OffsetReg);
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| H A D | SIRegisterInfo.cpp | 362 Register OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); local
366 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg)
372 .addReg(OffsetReg, RegState::Kill)
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| H A D | AMDGPUInstructionSelector.cpp | 2034 Register OffsetReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
2035 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), OffsetReg)
2039 [=](MachineInstrBuilder &MIB) { MIB.addReg(OffsetReg); }
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 130 unsigned OffsetReg; member in struct:__anon5205::LanaiOperand::MemOp
176 return Mem.OffsetReg;
616 Op->Mem.OffsetReg = 0;
624 unsigned OffsetReg = Op->getReg(); local
628 Op->Mem.OffsetReg = OffsetReg;
640 Op->Mem.OffsetReg = 0;
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 105 Register OffsetReg = MRI.createGenericVirtualRegister(s32); variable
106 MIRBuilder.buildConstant(OffsetReg, Offset);
109 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg);
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| H A D | Thumb2SizeReduction.cpp | 557 unsigned OffsetReg = 0; local
561 OffsetReg = MI->getOperand(2).getReg();
596 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
599 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) |
|
| H A D | Thumb2InstrInfo.cpp | 566 Register OffsetReg = MI.getOperand(FrameRegIdx + 1).getReg();
567 if (OffsetReg != 0) {
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | 114 Register OffsetReg = MRI.createGenericVirtualRegister(SType); variable
115 MIRBuilder.buildConstant(OffsetReg, Offset);
118 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg);
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| H A D | X86ISelLowering.cpp | [all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 241 unsigned OffsetReg; member in struct:__anon5338::SparcOperand::MemOp
302 return Mem.OffsetReg;
477 Op->Mem.OffsetReg = offsetReg;
486 Op->Mem.OffsetReg = Sparc::G0; // always 0
498 Op->Mem.OffsetReg = 0;
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64CallLowering.cpp | 159 Register OffsetReg = MRI.createGenericVirtualRegister(s64); variable
160 MIRBuilder.buildConstant(OffsetReg, Offset);
163 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg);
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| H A D | AArch64InstructionSelector.cpp | 4316 Register OffsetReg = OffsetInst->getOperand(1).getReg();
4326 std::swap(OffsetReg, ConstantReg);
4357 MachineInstr *ExtInst = getDefIgnoringCopies(OffsetReg, MRI);
4366 OffsetReg = ExtInst->getOperand(1).getReg();
4367 OffsetReg = narrowExtendRegIfNeeded(OffsetReg, MIB);
4373 [=](MachineInstrBuilder &MIB) { MIB.addUse(OffsetReg); },
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| H A D | AArch64FastISel.cpp | 94 unsigned OffsetReg = 0; member in class:__anon4909::final::Address
120 OffsetReg = Reg;
124 return OffsetReg;
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsCallLowering.cpp | 297 Register OffsetReg = MRI.createGenericVirtualRegister(s32); local
299 MIRBuilder.buildConstant(OffsetReg, Offset);
302 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg);
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| H A D | MipsSEInstrInfo.cpp | 873 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
881 Register OffsetReg = I->getOperand(0).getReg(); local
895 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg);
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| H A D | MipsISelLowering.cpp | 2549 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; local
2551 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2554 DAG.getRegister(OffsetReg, Ty),
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonOptAddrMode.cpp | 166 Register OffsetReg = MI.getOperand(2).getReg();
171 if (OffsetReg == RR.Reg) {
|
| H A D | HexagonISelLowering.cpp | 2867 unsigned OffsetReg = Hexagon::R28; local
2873 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
2876 // MF.getRegInfo().addLiveOut(OffsetReg);
|