Searched refs:NAE_REG (Results 1 - 8 of 8) sorted by relevance

/freebsd-12-stable/sys/mips/nlm/hal/
H A Dinterlaken.h41 #define ILK_TX_CONTROL(block) NAE_REG(block, 5, 0x00)
42 #define ILK_TX_RATE_LIMIT(block) NAE_REG(block, 5, 0x01)
43 #define ILK_TX_META_CTRL(block) NAE_REG(block, 5, 0x02)
44 #define ILK_RX_CTRL(block) NAE_REG(block, 5, 0x03)
45 #define ILK_RX_STATUS1(block) NAE_REG(block, 5, 0x04)
46 #define ILK_RX_STATUS2(block) NAE_REG(block, 5, 0x05)
47 #define ILK_GENERAL_CTRL1(block) NAE_REG(block, 5, 0x06)
48 #define ILK_STATUS3(block) NAE_REG(block, 5, 0x07)
49 #define ILK_RX_FC_TMAP0(block) NAE_REG(block, 5, 0x08)
50 #define ILK_RX_FC_TMAP1(block) NAE_REG(bloc
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H A Dnae.h43 #define NAE_REG(blk, intf, reg) (((blk) << 11) | ((intf) << 7) | (reg)) macro
46 #define NAE_RX_CONFIG NAE_REG(7, 0, 0x10)
47 #define NAE_RX_IF_BASE_CONFIG0 NAE_REG(7, 0, 0x12)
48 #define NAE_RX_IF_BASE_CONFIG1 NAE_REG(7, 0, 0x13)
49 #define NAE_RX_IF_BASE_CONFIG2 NAE_REG(7, 0, 0x14)
50 #define NAE_RX_IF_BASE_CONFIG3 NAE_REG(7, 0, 0x15)
51 #define NAE_RX_IF_BASE_CONFIG4 NAE_REG(7, 0, 0x16)
52 #define NAE_RX_IF_BASE_CONFIG5 NAE_REG(7, 0, 0x17)
53 #define NAE_RX_IF_BASE_CONFIG6 NAE_REG(7, 0, 0x18)
54 #define NAE_RX_IF_BASE_CONFIG7 NAE_REG(
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H A Dxaui.h40 #define XAUI_CONFIG0(block) NAE_REG(block, 4, 0x00)
41 #define XAUI_CONFIG1(block) NAE_REG(block, 4, 0x01)
42 #define XAUI_CONFIG2(block) NAE_REG(block, 4, 0x02)
43 #define XAUI_CONFIG3(block) NAE_REG(block, 4, 0x03)
45 #define XAUI_MAC_ADDR0_LO(block) NAE_REG(block, 4, 0x04)
46 #define XAUI_MAC_ADDR0_HI(block) NAE_REG(block, 4, 0x05)
48 #define XAUI_MAX_FRAME_LEN(block) NAE_REG(block, 4, 0x08)
49 #define XAUI_REVISION_LVL(block) NAE_REG(block, 4, 0x0b)
50 #define XAUI_MII_MGMT_CMD(block) NAE_REG(block, 4, 0x10)
51 #define XAUI_MII_MGMT_FIELD(block) NAE_REG(bloc
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H A Dsgmii.h42 #define SGMII_MAC_CONF1(block, i) NAE_REG(block, i, 0x00)
43 #define SGMII_MAC_CONF2(block, i) NAE_REG(block, i, 0x01)
44 #define SGMII_IPG_IFG(block, i) NAE_REG(block, i, 0x02)
45 #define SGMII_HLF_DUP(block, i) NAE_REG(block, i, 0x03)
46 #define SGMII_MAX_FRAME(block, i) NAE_REG(block, i, 0x04)
47 #define SGMII_TEST(block, i) NAE_REG(block, i, 0x07)
48 #define SGMII_MIIM_CONF(block, i) NAE_REG(block, i, 0x08)
49 #define SGMII_MIIM_CMD(block, i) NAE_REG(block, i, 0x09)
50 #define SGMII_MIIM_ADDR(block, i) NAE_REG(block, i, 0x0a)
51 #define SGMII_MIIM_CTRL(block, i) NAE_REG(bloc
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/freebsd-12-stable/sys/mips/nlm/dev/net/
H A Dmdio.c64 NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)));
67 NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus*4)),
72 NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
77 NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
82 NAE_REG(block, intf_type, (INT_MDIO_RD_STAT + bus * 4))) &
87 NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
92 NAE_REG(block, intf_type, (INT_MDIO_RD_STAT + bus * 4)));
114 NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)));
117 NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus*4)),
123 NAE_REG(bloc
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H A Dxaui.c67 NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_0_1));
77 NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_0_1),
83 NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_2_3));
93 NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_2_3),
121 reg = NAE_REG(block, PHY, lane_ctrl - 4);
H A Dsgmii.c56 nlm_write_nae_reg(nae_base, NAE_REG(block, port, MAC_CONF1), data1);
61 nlm_write_nae_reg(nae_base, NAE_REG(block, port, MAC_CONF2), data2);
65 nlm_write_nae_reg(nae_base, NAE_REG(block, port, MAC_CONF1), data1);
H A Dnae.c283 nlm_write_nae_reg(nae_base, NAE_REG(7, 0, id), val);
385 nlm_write_nae_reg(nae_base, NAE_REG(block, PHY, lane_ctrl), val);
393 NAE_REG(block, PHY, lane_ctrl));
399 NAE_REG(block, PHY, lane_ctrl), val);
405 NAE_REG(block, PHY, lane_ctrl), val);
412 NAE_REG(block, PHY, lane_ctrl)) & 0xFFC00000;
415 NAE_REG(block, PHY, lane_ctrl),
424 NAE_REG(block, PHY, lane_ctrl))) &
431 NAE_REG(block, PHY, lane_ctrl),
442 NAE_REG(bloc
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