Searched refs:MaskLo (Results 1 - 5 of 5) sorted by relevance
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorTypes.cpp | 1548 SDValue MaskLo, MaskHi; local 1550 SplitVecRes_SETCC(Mask.getNode(), MaskLo, MaskHi); 1553 GetSplitVector(Mask, MaskLo, MaskHi); 1555 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl); 1573 Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, Offset, MaskLo, PassThruLo, LoMemVT, 1577 Ptr = TLI.IncrementMemoryAddress(Ptr, MaskLo, dl, LoMemVT, DAG, 1616 SDValue MaskLo, MaskHi; local 1618 SplitVecRes_SETCC(Mask.getNode(), MaskLo, MaskHi); 1621 GetSplitVector(Mask, MaskLo, MaskHi); 1623 std::tie(MaskLo, MaskH 2249 SDValue MaskLo, MaskHi; local 2330 SDValue MaskLo, MaskHi; local 2392 SDValue MaskLo, MaskHi; local [all...] |
H A D | TargetLowering.cpp | 1659 APInt MaskLo = DemandedBits.getLoBits(HalfBitWidth).trunc(HalfBitWidth); local 1664 if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownLo, TLO, Depth + 1))
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUInstructionSelector.cpp | 1676 Register MaskLo = MRI->createVirtualRegister(&RegRC); 1683 BuildMI(*BB, &I, DL, TII.get(NewOpc), MaskLo) 1687 .addReg(MaskLo)
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H A D | AMDGPURegisterBankInfo.cpp | 1912 Register MaskLo = B.buildConstant(S32, 0xffff).getReg(0); local 1913 MRI.setRegBank(MaskLo, *BankLo); 1921 ZextLo = B.buildAnd(S32, Lo, MaskLo).getReg(0);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 21698 static const int MaskLo[] = { 0, 0, 2, 2 }; 21700 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo); [all...] |
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