/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600ControlFlowFinalizer.cpp | 352 MachineInstr *MIb = BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), local 356 return ClauseFile(MIb, std::move(ClauseContent)); 571 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), variable 576 Pair.second.insert(MIb); 596 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), variable 600 IfThenElseStack.push_back(MIb); 601 LLVM_DEBUG(dbgs() << CfCount << ":"; MIb->dump();); 610 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), variable 614 LLVM_DEBUG(dbgs() << CfCount << ":"; MIb->dump();); 615 IfThenElseStack.push_back(MIb); 625 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), variable 629 (void)MIb; variable 644 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), variable 652 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), variable [all...] |
H A D | SIInstrInfo.cpp | 2529 const MachineInstr &MIb) const { 2534 getMemOperandWithOffset(MIb, BaseOp1, Offset1, &RI)) { 2538 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) { 2543 unsigned Width1 = (*MIb.memoperands_begin())->getSize(); 2553 const MachineInstr &MIb) const { 2556 assert(MIb.mayLoadOrStore() && 2557 "MIb must load from or modify a memory location"); 2559 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects()) 2563 if (MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) 2572 if (isDS(MIb)) [all...] |
H A D | SIInstrInfo.h | 133 const MachineInstr &MIb) const; 316 const MachineInstr &MIb) const override;
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCDuplexInfo.cpp | 580 MCInst const &MIb, bool ExtendedB, 588 unsigned Opcode = MIb.getOpcode(); 593 MIbG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIb); 602 MCInst SubInst1 = HexagonMCInstrInfo::deriveSubInst(MIb); 616 if (MIb.getOpcode() == Hexagon::S2_allocframe) 621 // Note that MIb (slot1) can be extended and MIa (slot0) 628 if (subInstWouldBeExtended(MIb) && !ExtendedB) 632 // If jumpr r31 appears, it must be in slot 0, and never slot 1 (MIb). 634 if ((MIb.getNumOperands() > 1) && MIb 578 isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa, bool ExtendedA, MCInst const &MIb, bool ExtendedB, bool bisReversable, MCSubtargetInfo const &STI) argument 657 isDuplexPair(MCInst const &MIa, MCInst const &MIb) argument [all...] |
H A D | HexagonMCCompound.cpp | 335 MCInst const &MIb, bool IsExtendedB) { 337 unsigned MIbG = getCompoundCandidateGroup(MIb, IsExtendedB); 345 (MIa.getOperand(0).getReg() == MIb.getOperand(0).getReg())); 334 isOrderedCompoundPair(MCInst const &MIa, bool IsExtendedA, MCInst const &MIb, bool IsExtendedB) argument
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H A D | HexagonMCInstrInfo.h | 224 bool isDuplexPair(MCInst const &MIa, MCInst const &MIb); 259 bool ExtendedA, MCInst const &MIb, bool ExtendedB,
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiInstrInfo.h | 39 const MachineInstr &MIb) const override;
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H A D | LanaiInstrInfo.cpp | 89 const MachineInstr &MIa, const MachineInstr &MIb) const { 91 assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); 93 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || 94 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) 107 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrInfo.h | 95 const MachineInstr &MIb) const override;
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H A D | RISCVInstrInfo.cpp | 586 const MachineInstr &MIa, const MachineInstr &MIb) const { 588 assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); 590 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || 591 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) 604 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.h | 291 const MachineInstr &MIb) const override; 356 bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const;
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H A D | HexagonInstrInfo.cpp | 1871 const MachineInstr &MIa, const MachineInstr &MIb) const { 1872 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || 1873 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) 1878 if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb)) 1889 // Get the base register in MIb. 1891 if (!getBaseAndOffsetPosition(MIb, BasePosB, OffsetPosB)) 1893 const MachineOperand &BaseB = MIb.getOperand(BasePosB); 1902 unsigned SizeB = getMemAccessSize(MIb); 1906 const MachineOperand &OffB = MIb [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrInfo.h | 336 const MachineInstr &MIb) const override;
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H A D | SystemZInstrInfo.cpp | 1783 const MachineInstr &MIb) const { 1785 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) 1793 MachineMemOperand *MMOb = *MIb.memoperands_begin();
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64LoadStoreOptimizer.cpp | 1147 static bool mayAlias(MachineInstr &MIa, MachineInstr &MIb, 1150 if (!MIa.mayStore() && !MIb.mayStore()) 1154 if (!MIa.mayLoadOrStore() && !MIb.mayLoadOrStore()) 1157 return MIa.mayAlias(AA, MIb, /*UseTBAA*/false); 1163 for (MachineInstr *MIb : MemInsns) 1164 if (mayAlias(MIa, *MIb, AA))
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H A D | AArch64InstrInfo.h | 59 const MachineInstr &MIb) const override;
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H A D | AArch64InstrInfo.cpp | 933 const MachineInstr &MIa, const MachineInstr &MIb) const { 940 assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); 942 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || 943 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) 952 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.h | 371 const MachineInstr &MIb) const override;
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H A D | PPCInstrInfo.cpp | 4285 const MachineInstr &MIa, const MachineInstr &MIb) const { 4287 assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); 4289 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || 4290 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) 4303 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
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/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetInstrInfo.h | 1651 const MachineInstr &MIb) const { 1654 assert(MIb.mayLoadOrStore() && 1655 "MIb must load from or modify a memory location");
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/freebsd-12-stable/sys/cddl/dev/dtrace/x86/ |
H A D | dis_tables.c | 153 MIb, /* for 386 logicals */ enumerator in enum:__anon9863 557 /* [4] */ TS("bt",MIb), TS("bts",MIb), TS("btr",MIb), TS("btc",MIb), 3957 case MIb:
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