Searched refs:LiveIn (Results 1 - 22 of 22) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMachineFunctionInfo.cpp47 for (const std::pair<unsigned, ISD::ArgFlagsTy> &LiveIn : LiveInAttrs)
48 if (LiveIn.first == VReg)
49 return LiveIn.second.isSExt();
54 for (const std::pair<unsigned, ISD::ArgFlagsTy> &LiveIn : LiveInAttrs)
55 if (LiveIn.first == VReg)
56 return LiveIn.second.isZExt();
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveRangeCalc.h120 /// LiveIn - Work list of blocks where the live-in value has yet to be
124 SmallVector<LiveInBlock, 16> LiveIn; member in class:llvm::LiveRangeCalc
140 /// live in are added to the LiveIn array, and the function returns false.
152 /// blocks in LiveIn. Create PHI-def values as required to preserve SSA form.
158 /// Transfer information from the LiveIn vector to the live ranges and update
271 LiveIn.push_back(LiveInBlock(LR, DomNode, Kill));
H A DRDFLiveness.h137 void traverse(MachineBasicBlock *B, RefMap &LiveIn);
H A DMIRYamlMapping.h190 static void mapping(IO &YamlIO, MachineFunctionLiveIn &LiveIn) { argument
191 YamlIO.mapRequired("reg", LiveIn.Register);
193 "virtual-reg", LiveIn.VirtualRegister,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DSafeStackColoring.cpp112 BlockInfo.LiveIn.resize(NumAllocas);
169 // Compute LiveIn by unioning together the LiveOut sets of all preds.
190 // Update block LiveIn set, noting whether it has changed.
191 if (LocalLiveIn.test(BlockInfo.LiveIn)) {
193 BlockInfo.LiveIn |= LocalLiveIn;
218 // LiveIn ranges start at the first instruction.
220 if (BlockInfo.LiveIn.test(AllocaNo)) {
269 << ", livein " << BlockInfo.LiveIn << ", liveout "
H A DRDFLiveness.cpp802 RefMap LiveIn; local
803 traverse(&MF.front(), LiveIn);
874 BitVector LiveIn(TRI.getNumRegs()), Live(TRI.getNumRegs());
875 CopyLiveIns(B, LiveIn);
928 void Liveness::traverse(MachineBasicBlock *B, RefMap &LiveIn) { argument
929 // The LiveIn map, for each (physical) register, contains the set of live
960 LiveIn[S.first].insert(S.second.begin(), S.second.end());
969 dbgs() << " LiveIn: " << Print<RefMap>(LiveIn, DFG) << '\n';
976 LiveIn[
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H A DLiveRangeCalc.cpp61 LiveIn.clear();
218 for (const LiveInBlock &I : LiveIn) {
238 LiveIn.clear();
423 LiveIn.clear();
464 // Multiple values were found, so transfer the work list to the LiveIn array
466 LiveIn.reserve(WorkList.size());
474 LiveIn.back().Kill = Use;
492 for (LiveInBlock &I : LiveIn) {
H A DSafeStackColoring.h49 BitVector LiveIn; member in struct:llvm::safestack::StackColoring::BlockLifetimeInfo
H A DStackColoring.cpp396 BitVector LiveIn; member in struct:__anon4662::StackColoring::BlockLifetimeInfo
547 dumpBV("LIVE_IN", BlockInfo.LiveIn);
774 // Compute LiveIn by unioning together the LiveOut sets of all preds.
797 // Update block LiveIn set, noting whether it has changed.
798 if (LocalLiveIn.test(BlockInfo.LiveIn)) {
800 BlockInfo.LiveIn |= LocalLiveIn;
828 for (int pos = MBBLiveness.LiveIn.find_first(); pos != -1;
829 pos = MBBLiveness.LiveIn.find_next(pos)) {
H A DBranchRelaxation.cpp461 for (const MachineBasicBlock::RegisterMaskPair &LiveIn : Succ->liveins())
462 BranchBB->addLiveIn(LiveIn);
H A DMIRPrinter.cpp307 yaml::MachineFunctionLiveIn LiveIn; local
308 printRegMIR(LI.first, LiveIn.Register, TRI);
310 printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
311 MF.LiveIns.push_back(LiveIn);
H A DSplitKit.h125 bool LiveIn; ///< Current reg is live in. member in struct:llvm::SplitAnalysis::BlockInfo
H A DRegAllocGreedy.cpp1199 BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
1213 if (BI.LiveIn) {
1424 if (BI.LiveIn && BI.LiveOut && BI.FirstDef)
1601 if (EnableAdvancedRASplitCost && Cand.Intf.hasInterference() && BI.LiveIn &&
1622 if (BI.LiveIn)
1699 if (BI.LiveIn) {
2160 BI.LiveIn ? BI.FirstInstr.getBaseIndex() : BI.FirstInstr;
2341 const bool LiveBefore = SplitBefore != 0 || BI.LiveIn;
2435 bool LiveBefore = BestBefore != 0 || BI.LiveIn;
H A DMachineCSE.cpp690 auto LiveIn = PhysDefs.pop_back_val(); local
691 if (!MBB->isLiveIn(LiveIn.second))
692 MBB->addLiveIn(LiveIn.second);
H A DRegisterPressure.cpp916 LaneBitmask LiveIn = Use.LaneMask & ~LiveMask;
917 if (LiveIn.any()) {
918 discoverLiveIn(RegisterMaskPair(Reg, LiveIn));
919 increaseRegPressure(Reg, LiveMask, LiveMask | LiveIn);
920 LiveRegs.insert(RegisterMaskPair(Reg, LiveIn));
1335 /// This assumes that the current LiveIn set is sufficient.
H A DSplitKit.cpp253 BI.LiveIn = LVI->start <= Start;
256 if (!BI.LiveIn) {
283 BI.LiveIn = false;
1565 if (BI.LiveIn && BI.LiveOut)
1715 assert(BI.LiveIn && "Must be live-in");
1805 << (BI.LiveIn ? ", stack-in" : ", defined in block"));
1813 if (!BI.LiveIn && (!EnterAfter || EnterAfter <= BI.FirstInstr)) {
H A DMachineBasicBlock.cpp500 bool LiveIn = isLiveIn(PhysReg);
506 if (LiveIn)
519 if (!LiveIn)
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/
H A DMIRParser.cpp552 for (const auto &LiveIn : YamlMF.LiveIns) {
554 if (parseNamedRegisterReference(PFS, Reg, LiveIn.Register.Value, Error))
555 return error(Error, LiveIn.Register.SourceRange);
557 if (!LiveIn.VirtualRegister.Value.empty()) {
559 if (parseVirtualRegisterReference(PFS, Info, LiveIn.VirtualRegister.Value,
561 return error(Error, LiveIn.VirtualRegister.SourceRange);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DRewriteStatepointsForGC.cpp243 MapVector<BasicBlock *, SetVector<Value *>> LiveIn; member in struct:__anon5713::GCPtrLivenessData
2643 // KILL/Def - Remove this definition from LiveIn
2651 // USE - Add to the LiveIn set for this instruction
2721 checkBasicSSA(DT, Data.LiveIn[&BB], BB.getTerminator());
2742 Data.LiveIn[&BB] = Data.LiveSet[&BB];
2743 Data.LiveIn[&BB].set_union(Data.LiveOut[&BB]);
2744 Data.LiveIn[&BB].set_subtract(Data.KillSet[&BB]);
2745 if (!Data.LiveIn[&BB].empty())
2758 assert(Data.LiveIn.count(Succ));
2759 LiveOut.set_union(Data.LiveIn[Suc
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNSchedStrategy.cpp472 auto LiveIn = std::move(LiveInIt->second); local
473 RPTracker.reset(*MBB->begin(), &LiveIn);
H A DAMDGPULegalizerInfo.cpp1832 Register LiveIn = MRI.getLiveInVirtReg(Reg);
1833 if (LiveIn)
1834 return LiveIn;
1851 Register LiveIn = getLiveInRegister(MRI, Arg->getRegister(), Ty);
1859 Register AndMaskSrc = LiveIn;
1863 AndMaskSrc = B.buildLShr(S32, LiveIn, ShiftAmt).getReg(0);
1868 B.buildCopy(DstReg, LiveIn);
1872 if (!MRI.getVRegDef(LiveIn)) {
1880 B.buildCopy(LiveIn, Arg->getRegister());
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DIRTranslator.cpp2417 for (const MachineBasicBlock::RegisterMaskPair &LiveIn : EntryBB->liveins())
2418 NewEntryBB.addLiveIn(LiveIn);

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