| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 35 LSR, enumerator in enum:llvm::AArch64_AM::ShiftExtendType
56 case AArch64_AM::LSR: return "lsr";
77 case 1: return AArch64_AM::LSR;
105 case AArch64_AM::LSR: STEnc = 1; break;
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.h | 39 LSR, ///< Logical shift right. enumerator in enum:llvm::AVRISD::NodeType
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| H A D | AVRISelLowering.cpp | 256 NODE(LSR);
323 Opc8 = AVRISD::LSR;
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| /freebsd-12-stable/contrib/llvm-project/lldb/source/Plugins/Process/Utility/ |
| H A D | ARMUtils.h | 124 static inline uint32_t LSR(const uint32_t value, const uint32_t amount, function in namespace:lldb_private
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 453 LSR, enumerator in enum:llvm::AArch64SE::ShiftExtSpecifiers
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AsmPrinter.cpp | 389 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56)),
460 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56)),
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| H A D | AArch64ISelDAGToDAG.cpp | 402 return AArch64_AM::LSR;
2024 } else if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSR) {
2185 // LSR wD, wN, #Amt == UBFM wD, wN, #Amt, #32-1
2238 // LSL/LSR if the mask in NonZeroBits doesn't quite match up with the ISD::SHL
2486 SDNode *LSR = CurDAG->getMachineNode( local
2495 SDValue Ops[] = {Dst, SDValue(LSR, 0),
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| H A D | AArch64FastISel.cpp | 1283 case Instruction::LShr: ShiftType = AArch64_AM::LSR; break;
3800 /*IsKill=*/false, AArch64_AM::LSR, 32,
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| H A D | AArch64InstructionSelector.cpp | 4665 return AArch64_AM::LSR;
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1208 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR ||
1301 // An arithmetic shifter is LSL, LSR, or ASR.
1303 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR ||
1312 // A logical shifter is LSL, LSR, ASR or ROR.
1314 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR ||
2746 .Case("lsr", AArch64_AM::LSR)
2769 if (ShOp == AArch64_AM::LSL || ShOp == AArch64_AM::LSR ||
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| /freebsd-12-stable/secure/lib/libcrypto/arm/ |
| H A D | bsaes-armv7.S | 565 .LSR:
919 vldmia r6, {q12} @ .LSR
1434 mov r6, #:lower16:(.LREVM0SR-.LSR)
1437 sub r6, r8, #.LREVM0SR-.LSR @ pass constants
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 2709 LatticeCell LSR; local
2710 if (!evaluate(R, LR, LSR))
2712 RC.meet(LSR);
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| /freebsd-12-stable/crypto/openssl/crypto/aes/asm/ |
| H A D | bsaes-armv7.pl | 827 .LSR:
894 vldmia $const, {@XMM[12]} @ .LSR
1486 mov $const, #:lower16:(.LREVM0SR-.LSR)
1489 sub $const, $ctr, #.LREVM0SR-.LSR @ pass constants
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