Searched refs:L1_S_C (Results 1 - 7 of 7) sorted by relevance

/freebsd-12-stable/sys/arm/include/
H A Dpte-v6.h117 #define L1_S_C 0x00000008 /* cacheable Section */ macro
170 #define TEX1_CLASS_2 ( L1_S_C )
171 #define TEX1_CLASS_3 ( L1_S_C | L1_S_B)
174 #define TEX1_CLASS_6 (L1_S_TEX0 | L1_S_C ) /* Reserved for ARM11 */
175 #define TEX1_CLASS_7 (L1_S_TEX0 | L1_S_C | L1_S_B)
229 #define PTE1_ATTR_MASK (L1_S_TEX0 | L1_S_C | L1_S_B)
H A Dpte-v4.h171 #define L1_S_C 0x00000008 /* cacheable Section */ macro
H A Dpmap-v4.h254 #define L1_S_CACHE_MASK (L1_S_B|L1_S_C)
/freebsd-12-stable/sys/arm/arm/
H A Dlocore-v4.S324 ldr r4, =(L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
H A Delf_trampoline.c461 pd[addr >> L1_S_SHIFT] = L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)|
H A Dpmap-v4.c451 pte_l1_s_cache_mode = L1_S_B|L1_S_C;
466 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
470 pte_l1_s_cache_mode_pt = L1_S_C;
H A Dpmap-v6.c192 (((l2_attr) & L2_C) ? L1_S_C : 0) | \
204 (((l1_attr) & L1_S_C) ? L2_C : 0) | \

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