Searched refs:InsInstrs (Results 1 - 5 of 5) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineCombiner.cpp94 unsigned getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
102 SmallVectorImpl<MachineInstr *> &InsInstrs,
108 SmallVectorImpl<MachineInstr *> &InsInstrs,
114 SmallVectorImpl<MachineInstr *> &InsInstrs,
158 /// \param InsInstrs is a vector of machine instructions
160 /// of defining machine instruction in \p InsInstrs
163 /// \returns Depth of last instruction in \InsInstrs ("NewRoot")
165 MachineCombiner::getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs, argument
175 for (auto *InstrPtr : InsInstrs) { // for each Use
190 MachineInstr *DefInstr = InsInstrs[I
282 getLatenciesForInstrSequences( MachineInstr &MI, SmallVectorImpl<MachineInstr *> &InsInstrs, SmallVectorImpl<MachineInstr *> &DelInstrs, MachineTraceMetrics::Trace BlockTrace) argument
306 improvesCriticalPathLen( MachineBasicBlock *MBB, MachineInstr *Root, MachineTraceMetrics::Trace BlockTrace, SmallVectorImpl<MachineInstr *> &InsInstrs, SmallVectorImpl<MachineInstr *> &DelInstrs, DenseMap<unsigned, unsigned> &InstrIdxForVirtReg, MachineCombinerPattern Pattern, bool SlackIsAccurate) argument
[all...]
H A DTargetInstrInfo.cpp775 SmallVectorImpl<MachineInstr *> &InsInstrs,
850 InsInstrs.push_back(MIB1);
851 InsInstrs.push_back(MIB2);
858 SmallVectorImpl<MachineInstr *> &InsInstrs,
880 reassociateOps(Root, *Prev, Pattern, InsInstrs, DelInstrs, InstIdxForVirtReg);
772 reassociateOps( MachineInstr &Root, MachineInstr &Prev, MachineCombinerPattern Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs, SmallVectorImpl<MachineInstr *> &DelInstrs, DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const argument
856 genAlternativeCodeSequence( MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs, SmallVectorImpl<MachineInstr *> &DelInstrs, DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const argument
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp4158 /// \param [out] InsInstrs is a vector of machine instructions and will
4170 SmallVectorImpl<MachineInstr *> &InsInstrs, unsigned IdxMulOpd,
4224 InsInstrs.push_back(MIB);
4234 MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs,
4236 return genFusedMultiply(MF, MRI, TII, Root, InsInstrs, IdxMulOpd, MaddOpc, RC,
4244 SmallVectorImpl<MachineInstr *> &InsInstrs,
4251 InsInstrs.push_back(MIB);
4263 MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs,
4269 genNeg(MF, MRI, TII, Root, InsInstrs, InstrIdxForVirtReg, MnegOpc, RC);
4270 return genFusedMultiply(MF, MRI, TII, Root, InsInstrs, IdxMulOp
4168 genFusedMultiply(MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, const TargetRegisterClass *RC, FMAInstKind kind = FMAInstKind::Default, const Register *ReplacedAddend = nullptr) argument
4232 genFusedMultiplyAcc( MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, const TargetRegisterClass *RC) argument
4242 genNeg(MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs, DenseMap<unsigned, unsigned> &InstrIdxForVirtReg, unsigned MnegOpc, const TargetRegisterClass *RC) argument
4261 genFusedMultiplyAccNeg( MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs, DenseMap<unsigned, unsigned> &InstrIdxForVirtReg, unsigned IdxMulOpd, unsigned MaddOpc, unsigned MnegOpc, const TargetRegisterClass *RC) argument
4278 genFusedMultiplyIdx( MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, const TargetRegisterClass *RC) argument
4288 genFusedMultiplyIdxNeg( MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs, DenseMap<unsigned, unsigned> &InstrIdxForVirtReg, unsigned IdxMulOpd, unsigned MaddOpc, unsigned MnegOpc, const TargetRegisterClass *RC) argument
4321 genMaddR(MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, unsigned VR, const TargetRegisterClass *RC) argument
4357 genAlternativeCodeSequence( MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs, SmallVectorImpl<MachineInstr *> &DelInstrs, DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const argument
[all...]
H A DAArch64InstrInfo.h235 SmallVectorImpl<MachineInstr *> &InsInstrs,
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1077 /// \param InsInstrs - Vector of new instructions that implement P
1084 SmallVectorImpl<MachineInstr *> &InsInstrs,
1092 SmallVectorImpl<MachineInstr *> &InsInstrs,

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