/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyRuntimeLibcallSignatures.cpp | 520 Subtarget.hasAddr64() ? wasm::ValType::I64 : wasm::ValType::I32; 540 Params.push_back(wasm::ValType::I64); 560 Params.push_back(wasm::ValType::I64); 575 Rets.push_back(wasm::ValType::I64); 579 Rets.push_back(wasm::ValType::I64); 583 Rets.push_back(wasm::ValType::I64); 584 Params.push_back(wasm::ValType::I64); 598 Params.push_back(wasm::ValType::I64); 599 Params.push_back(wasm::ValType::I64); 613 Params.push_back(wasm::ValType::I64); [all...] |
H A D | WebAssemblyMCInstLower.cpp | 111 Params.push_back(Subtarget.hasAddr64() ? wasm::ValType::I64 186 return wasm::ValType::I64;
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/freebsd-12-stable/tools/tools/nanobsd/rescue/ |
H A D | merge.sh | 7 I64="/usr/obj/Rescue/rescue_${today}_x64.img"
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
H A D | WebAssemblyMCTargetDesc.cpp | 138 return wasm::ValType::I64;
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H A D | WebAssemblyMCTargetDesc.h | 130 I64 = unsigned(wasm::ValType::I64), member in class:llvm::WebAssembly::BlockType
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/freebsd-12-stable/contrib/binutils/opcodes/ |
H A D | mips16-opc.c | 64 #define I64 INSN_ISA64 macro 237 {"sew", "x", 0xe8d1, 0xf8ff, WR_x|RD_x, 0, I64 }, 240 {"zew", "x", 0xe851, 0xf8ff, WR_x|RD_x, 0, I64 },
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H A D | mips-opc.c | 88 #define I64 INSN_ISA64 macro 529 {"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, 530 {"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, 584 {"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, 585 {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, 589 {"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 }, 590 {"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 }, 1409 {"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 }, 1412 {"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 },
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/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/BinaryFormat/ |
H A D | Wasm.h | 349 I64 = WASM_TYPE_I64, member in class:llvm::wasm::ValType
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/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Support/ |
H A D | AMDGPUMetadata.h | 93 I64 = 9, member in class:llvm::AMDGPU::HSAMD::AccessQualifier::AddressSpaceQualifier::ValueKind::ValueType
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULibFunc.h | 268 I64 = INT | B64, enumerator in enum:llvm::AMDGPULibFuncBase::EType
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H A D | AMDGPULibFunc.cpp | 630 case 'l': res.ArgType = AMDGPULibFunc::I64; break; 736 case AMDGPULibFunc::I64: return "l"; 885 case AMDGPULibFunc::I64: T = Type::getInt64Ty(C); break;
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H A D | AMDGPUHSAMetadataStreamer.cpp | 142 return Signed ? ValueType::I64 : ValueType::U64;
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Support/ |
H A D | AMDGPUMetadata.cpp | 86 YIO.enumCase(EN, "I64", ValueType::I64);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/AsmParser/ |
H A D | WebAssemblyAsmParser.cpp | 302 return wasm::ValType::I64; 320 .Case("i64", WebAssembly::BlockType::I64)
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/ObjectYAML/ |
H A D | WasmYAML.cpp | 557 ECase(I64);
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/freebsd-12-stable/contrib/binutils/gas/config/ |
H A D | tc-arm.c | 11842 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not 16037 shl_imm should accept I8 I16 I32 I64, 16088 /* Add/sub take types I8 I16 I32 I64 F32. */ 16125 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), 16126 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), 16127 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), 16128 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), 16132 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), 16133 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), 16144 /* Right shift narrowing. Types accepted I16 I32 I64 [all...] |
/freebsd-12-stable/contrib/llvm-project/clang/lib/CodeGen/ |
H A D | TargetInfo.cpp | 7154 llvm::IntegerType *I64 = llvm::IntegerType::get(getVMContext(), 64); 7172 ArgList.push_back(I64);
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