| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ValueTypes.h | 348 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); local
349 if (HalfVT.getSizeInBits() * 2 >= EVTSize)
350 return HalfVT;
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 1643 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext()); local
1645 SDValue One = DAG.getConstant(1, DL, HalfVT);
1646 SDValue Zero = DAG.getConstant(0, DL, HalfVT);
1650 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1651 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, One);
1654 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1655 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, One);
1660 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1694 SDValue Rcp_Lo = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Mad
1982 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext()); local
[all...] |
| H A D | SIISelLowering.cpp | 4984 EVT HalfVT = MVT::getVectorVT(VT.getVectorElementType().getSimpleVT(), 2);
4988 SDValue Lo = DAG.getBuildVector(HalfVT, SL,
4990 SDValue Hi = DAG.getBuildVector(HalfVT, SL,
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeTypes.cpp | 1014 EVT HalfVT = local
1016 SplitInteger(Op, HalfVT, HalfVT, Lo, Hi);
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| H A D | LegalizeVectorTypes.cpp | 2560 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, local
2567 HalfLo = DAG.getNode(N->getOpcode(), DL, {HalfVT, MVT::Other},
2569 HalfHi = DAG.getNode(N->getOpcode(), DL, {HalfVT, MVT::Other},
2576 HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec);
2577 HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec);
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| H A D | TargetLowering.cpp | 1656 EVT HalfVT = Op.getOperand(0).getValueType(); local
1657 unsigned HalfBitWidth = HalfVT.getScalarSizeInBits();
7640 EVT HalfVT = VT.getHalfNumVectorElementsVT(*DAG.getContext());
7641 if (!isOperationLegalOrCustom(BaseOpcode, HalfVT))
7646 Op = DAG.getNode(BaseOpcode, dl, HalfVT, Lo, Hi);
7647 VT = HalfVT;
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| H A D | DAGCombiner.cpp | 4738 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), Size / 2); local
4744 TLI.isNarrowingProfitable(VT, HalfVT) &&
4745 TLI.isTypeDesirableForOp(ISD::AND, HalfVT) &&
4746 TLI.isTypeDesirableForOp(ISD::SRL, HalfVT) &&
4747 TLI.isTruncateFree(VT, HalfVT) &&
4748 TLI.isZExtFree(HalfVT, VT)) {
4758 EVT ShiftVT = TLI.getShiftAmountTy(HalfVT, DAG.getDataLayout());
4759 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, HalfVT,
4762 SDValue NewMask = DAG.getConstant(AndMask.trunc(Size / 2), SL, HalfVT);
4764 SDValue Shift = DAG.getNode(ISD::SRL, SL, HalfVT, Trun
[all...] |
| H A D | LegalizeIntegerTypes.cpp | 3547 EVT HalfVT = LHSLow.getValueType() local
3549 SDVTList VTHalfMulO = DAG.getVTList(HalfVT, BitVT);
3552 SDValue HalfZero = DAG.getConstant(0, dl, HalfVT);
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| H A D | SelectionDAGBuilder.cpp | 231 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); local
235 PartVT, HalfVT, V);
237 RoundParts / 2, PartVT, HalfVT, V);
239 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
240 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InterleavedAccess.cpp | 367 MVT HalfVT = scaleVectorType(VT); local
385 createUnpackShuffleMask<uint32_t>(HalfVT, MaskLowTemp, true, false);
386 createUnpackShuffleMask<uint32_t>(HalfVT, MaskHighTemp, false, false);
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| H A D | X86ISelLowering.cpp | 8232 EVT HalfVT =
8235 EltsFromConsecutiveLoads(HalfVT, Elts.drop_back(HalfNumElems), DL,
9322 MVT HalfVT = VT.getHalfNumVectorElementsVT();
9325 SDValue Half = DAG.getNode(HOpcode, SDLoc(BV), HalfVT, V0, V1);
10246 MVT HalfVT = ResVT.getHalfNumVectorElementsVT();
10248 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT,
10250 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT,
10335 MVT HalfVT = ResVT.getHalfNumVectorElementsVT();
10337 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT,
10339 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT,
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 8974 auto *HalfVT = cast<VectorType>(HalfV->getType());
8975 return FullVT->getBitWidth() == 2 * HalfVT->getBitWidth();
8980 auto *HalfVT = cast<VectorType>(HalfV->getType());
8981 return FullVT->getNumElements() == 2 * HalfVT->getNumElements();
11469 EVT HalfVT = VT.getHalfNumVectorElementsVT(*DAG.getContext()); local
11470 unsigned NumElts = HalfVT.getVectorNumElements();
11471 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
11473 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
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