/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86CmovConversion.cpp | 715 Register FalseReg = local 719 auto FRIt = FalseBBRegRewriteTable.find(FalseReg); 722 FalseReg = FRIt->second; 724 FalseBBRegRewriteTable[MI.getOperand(0).getReg()] = FalseReg;
|
H A D | X86InstrInfo.h | 313 unsigned FalseReg) const override;
|
H A D | X86InstrInfo.cpp | 2832 unsigned TrueReg, unsigned FalseReg, 2846 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 2870 unsigned FalseReg) const { 2878 .addReg(FalseReg) 2830 canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
|
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiInstrInfo.cpp | 506 MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2); 508 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); 531 // allocator ensure the FalseReg is allocated the same register as operand 0. 532 FalseReg.setImplicit(); 533 NewMI.add(FalseReg);
|
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrInfo.h | 229 unsigned FalseReg) const override;
|
H A D | SystemZInstrInfo.cpp | 535 unsigned TrueReg, unsigned FalseReg, 547 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 571 unsigned FalseReg) const { 591 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg); 593 FalseReg = FReg; 604 .addReg(FalseReg).addReg(TrueReg) 533 canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Pred, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
|
H A D | SystemZISelLowering.cpp | 6815 Register FalseReg = MI->getOperand(2).getReg(); local 6821 std::swap(TrueReg, FalseReg); 6826 if (RegRewriteTable.find(FalseReg) != RegRewriteTable.end()) 6827 FalseReg = RegRewriteTable[FalseReg].second; 6832 .addReg(FalseReg).addMBB(FalseMBB); 6835 RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg); 6920 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
|
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrInfo.h | 198 unsigned FalseReg) const override;
|
H A D | AArch64InstrInfo.cpp | 499 unsigned TrueReg, unsigned FalseReg, 505 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 521 else if (canFoldIntoCSel(MRI, FalseReg)) 543 unsigned TrueReg, unsigned FalseReg) const { 649 // FalseReg, so we need to invert the condition. 651 TrueReg = FalseReg; 653 FoldedOpc = canFoldIntoCSel(MRI, FalseReg, &NewVReg); 657 FalseReg = NewVReg; 666 MRI.constrainRegClass(FalseReg, RC); 671 .addReg(FalseReg) 497 canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.h | 297 unsigned TrueReg, unsigned FalseReg, 304 unsigned TrueReg, unsigned FalseReg) const override; 309 unsigned TrueReg, unsigned FalseReg) const;
|
H A D | SIInstrInfo.cpp | 824 unsigned FalseReg) const { 839 .addReg(FalseReg) 854 .addReg(FalseReg) 868 .addReg(FalseReg) 882 .addReg(FalseReg) 898 .addReg(FalseReg) 914 .addReg(FalseReg) 932 .addReg(FalseReg) 2128 unsigned TrueReg, unsigned FalseReg, 2136 assert(MRI.getRegClass(FalseReg) 2126 canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 757 unsigned TrueReg, unsigned FalseReg, 770 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 796 unsigned FalseReg) const { 803 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 804 assert(RC && "TrueReg and FalseReg must have overlapping register classes"); 855 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, 856 SecondReg = SwapOps ? TrueReg : FalseReg; 2224 unsigned TrueReg, unsigned FalseReg, 2231 return Imm1 < Imm2 ? TrueReg : FalseReg; 2233 return Imm1 > Imm2 ? TrueReg : FalseReg; 755 canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument [all...] |
H A D | PPCInstrInfo.h | 280 unsigned FalseReg) const override;
|
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMInstructionSelector.cpp | 790 auto FalseReg = MIB->getOperand(3).getReg(); local 792 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && 797 .addUse(FalseReg)
|
H A D | ARMBaseInstrInfo.cpp | 2245 MachineOperand FalseReg = MI.getOperand(Invert ? 2 : 1); 2247 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); 2275 // The tie makes the register allocator ensure the FalseReg is allocated the 2277 FalseReg.setImplicit(); 2278 NewMI.add(FalseReg);
|
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyFastISel.cpp | 899 unsigned FalseReg = getRegForValue(Select->getFalseValue()); local 900 if (FalseReg == 0) 904 std::swap(TrueReg, FalseReg); 939 .addReg(FalseReg)
|
H A D | WebAssemblyISelLowering.cpp | 387 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; local 392 FalseReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg)); 425 BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg).addReg(InReg); 429 .addReg(FalseReg)
|
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetInstrInfo.h | 830 /// instruction that chooses between TrueReg and FalseReg based on the 834 /// FalseReg, and Cond to the destination register. In most cases, a select 842 /// @param FalseReg Virtual register to select when Cond is false. 845 /// @param FalseCycles Latency from FalseReg to select output. 848 unsigned FalseReg, int &CondCycles, 854 /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false. 867 /// @param FalseReg Virtual register to copy when Cons is false. 871 unsigned TrueReg, unsigned FalseReg) const { 846 canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
|