Searched refs:ExtReg (Results 1 - 9 of 9) sorted by relevance
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsCallLowering.cpp | 281 Register ExtReg = extendRegister(ValVReg, VA); local 282 MIRBuilder.buildCopy(PhysReg, ExtReg); 317 Register ExtReg = extendRegister(ValVReg, VA); local 318 MIRBuilder.buildStore(ExtReg, Addr, *MMO); 326 Register ExtReg = MRI.createGenericVirtualRegister(LocTy); local 327 MIRBuilder.buildSExt(ExtReg, ValReg); 328 return ExtReg; 331 Register ExtReg = MRI.createGenericVirtualRegister(LocTy); local 332 MIRBuilder.buildZExt(ExtReg, ValReg); 333 return ExtReg; 336 Register ExtReg = MRI.createGenericVirtualRegister(LocTy); local [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86CallLowering.cpp | 128 Register ExtReg; variable 142 ExtReg = MIB->getOperand(0).getReg(); 144 ExtReg = extendRegister(ValVReg, VA); 146 MIRBuilder.buildCopy(PhysReg, ExtReg); 151 Register ExtReg = extendRegister(ValVReg, VA); variable 155 MIRBuilder.buildStore(ExtReg, Addr, *MMO);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMCallLowering.cpp | 123 Register ExtReg = extendRegister(ValVReg, VA); variable 124 MIRBuilder.buildCopy(PhysReg, ExtReg); 133 Register ExtReg = extendRegister(ValVReg, VA); variable 137 MIRBuilder.buildStore(ExtReg, Addr, *MMO);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUCallLowering.cpp | 54 Register ExtReg; variable 58 ExtReg = MIRBuilder.buildAnyExt(LLT::scalar(32), ValVReg).getReg(0); 60 ExtReg = extendRegister(ValVReg, VA); 62 MIRBuilder.buildCopy(PhysReg, ExtReg);
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H A D | AMDGPUInstructionSelector.cpp | 1383 Register ExtReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass); 1386 BuildMI(MBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), ExtReg) 1393 .addReg(ExtReg)
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64InstructionSelector.cpp | 256 /// being extended to be a GPR32. Narrow ExtReg to a 32-bit register using a 257 /// subregister copy if necessary. Return either ExtReg, or the result of the 259 Register narrowExtendRegIfNeeded(Register ExtReg, 4539 Register ExtReg = 4543 // Base is LHS, offset is ExtReg. 4545 [=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }, 4771 Register ExtReg, MachineIRBuilder &MIB) const { 4773 if (MRI.getType(ExtReg).getSizeInBits() == 32) 4774 return ExtReg; 4776 // Insert a copy to move ExtReg t [all...] |
H A D | AArch64CallLowering.cpp | 172 Register ExtReg = extendRegister(ValVReg, VA); variable 173 MIRBuilder.buildCopy(PhysReg, ExtReg);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 934 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass); local 935 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) 937 SrcReg1 = ExtReg; 940 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass); local 941 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) 943 SrcReg2 = ExtReg;
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H A D | PPCISelLowering.cpp | 10736 Register ExtReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); local 10738 ExtReg).addReg(dest); 10740 .addReg(incr).addReg(ExtReg);
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