Searched refs:EVERGREEN_CRTC4_REGISTER_OFFSET (Results 1 - 6 of 6) sorted by relevance

/freebsd-12-stable/sys/dev/drm2/radeon/
H A Devergreen_reg.h217 #define EVERGREEN_CRTC4_REGISTER_OFFSET (0x11df0 - 0x6df0) macro
H A Devergreen.c47 EVERGREEN_CRTC4_REGISTER_OFFSET,
2605 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2616 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2674 afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2814 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2825 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2840 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5);
2863 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2871 rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2904 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEA
[all...]
H A Dsi.c3323 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3334 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3551 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
3562 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
3593 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
3627 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3631 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
3633 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
H A Dradeon_display.c1286 rdev->mode_info.afmt[4]->offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1595 EVERGREEN_CRTC4_REGISTER_OFFSET);
1597 EVERGREEN_CRTC4_REGISTER_OFFSET);
H A Dradeon_device.c450 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
H A Datombios_crtc.c1921 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;

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