Searched refs:EVERGREEN_CRTC2_REGISTER_OFFSET (Results 1 - 6 of 6) sorted by relevance

/freebsd-12-stable/sys/dev/drm2/radeon/
H A Devergreen_reg.h215 #define EVERGREEN_CRTC2_REGISTER_OFFSET (0x105f0 - 0x6df0) macro
H A Devergreen.c45 EVERGREEN_CRTC2_REGISTER_OFFSET,
2601 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2612 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2672 afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2810 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2821 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2838 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3);
2859 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2869 rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2889 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEA
[all...]
H A Dsi.c3319 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3330 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3547 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
3558 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
3589 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
3612 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3616 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
3618 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
H A Dradeon_display.c1274 rdev->mode_info.afmt[2]->offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1581 EVERGREEN_CRTC2_REGISTER_OFFSET);
1583 EVERGREEN_CRTC2_REGISTER_OFFSET);
H A Dradeon_device.c448 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
H A Datombios_crtc.c1915 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;

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