Searched refs:DstRegBank (Results 1 - 3 of 3) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 922 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); local
929 assert(DstRegBank.getID() == ARM::GPRRegBankID &&
949 if (SrcRegBank.getID() != DstRegBank.getID()) {
1017 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); local
1019 if (SrcRegBank.getID() != DstRegBank.getID()) {
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | 235 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); local
245 DstRegBank.getID() == X86::GPRRegBankID) {
278 getRegClass(MRI.getType(DstReg), DstRegBank);
281 DstRegBank.getID() == X86::GPRRegBankID && SrcSize > DstSize &&
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstructionSelector.cpp | 650 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); local
663 if (SrcRegBank != DstRegBank && (DstSize == 1 && SrcSize == 1))
667 getMinClassForRegBank(DstRegBank, DstSize, true)};
676 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); local
706 assert(KnownValid || isValidCopy(I, DstRegBank, MRI, TRI, RBI));
730 getMinClassForRegBank(DstRegBank, SrcSize, true);
746 if (DstRegBank.getID() != SrcRegBank.getID()) {
747 if (DstRegBank.getID() == AArch64::GPRRegBankID && DstSize == 32 &&
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