Searched refs:DestRC (Results 1 - 5 of 5) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXInstrInfo.cpp | 37 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg); local
40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC))
44 if (DestRC == &NVPTX::Int1RegsRegClass) {
46 } else if (DestRC == &NVPTX::Int16RegsRegClass) {
48 } else if (DestRC == &NVPTX::Int32RegsRegClass) {
51 } else if (DestRC == &NVPTX::Int64RegsRegClass) {
54 } else if (DestRC == &NVPTX::Float16RegsRegClass) {
57 } else if (DestRC == &NVPTX::Float16x2RegsRegClass) {
59 } else if (DestRC == &NVPTX::Float32RegsRegClass) {
62 } else if (DestRC
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGFast.cpp | 381 const TargetRegisterClass *DestRC,
386 CopyFromSU->CopyDstRC = DestRC;
389 CopyToSU->CopySrcRC = DestRC;
575 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); local
585 if (DestRC != RC) {
587 if (!DestRC && !NewDef)
594 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
380 InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, SmallVectorImpl<SUnit*> &Copies) argument
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| H A D | ScheduleDAGRRList.cpp | 1223 const TargetRegisterClass *DestRC,
1228 CopyFromSU->CopyDstRC = DestRC;
1231 CopyToSU->CopySrcRC = DestRC;
1559 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); local
1569 if (DestRC != RC) {
1571 if (!DestRC && !NewDef)
1577 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
1222 InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, SmallVectorImpl<SUnit*> &Copies) argument
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 643 const TargetRegisterClass *DestRC = MRI->getRegClass(DestReg); local
648 if (TRI->isSGPRClass(SrcRC) && TRI->hasVectorRegisters(DestRC)) {
666 if (DestRC == &AMDGPU::AGPR_32RegClass &&
677 unsigned MovOp = TII->getMovOpcode(DestRC);
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| H A D | SIInstrInfo.cpp | 5317 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
5318 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
5455 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
5456 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
5498 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
5516 Register NewDest = MRI.createVirtualRegister(DestRC);
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