| /freebsd-12-stable/crypto/openssl/crypto/chacha/asm/ |
| H A D | chacha-armv8.pl | 700 $A3,$B3,$C3,$D3,$A4,$B4,$C4,$D4,$A5,$B5,$C5,$D5) = map("v$_.4s",(0..23));
786 add $D5,$D1,$ONE // +4
807 my @thread5=&NEONROUND($A5,$B5,$C5,$D5,$T5,0);
826 @thread5=&NEONROUND($A5,$B5,$C5,$D5,$T5,1);
921 @thread5=&NEONROUND($A5,$B5,$C5,$D5,$T5,0);
938 @thread5=&NEONROUND($A5,$B5,$C5,$D5,$T5,1);
985 add $D5,$D5,$ONE // +4
997 add $D5,$D5,
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 77 case D7: case D6: case D5: case D4:
|
| H A D | ARMCallingConv.cpp | 163 ARM::D4, ARM::D5, ARM::D6, ARM::D7 };
|
| /freebsd-12-stable/lib/msun/ld128/ |
| H A D | s_expl.c | 177 D5 = 8.33333333333333333333333364022244481e-3L, variable
253 q = x * x2 * D3 + x2 * x2 * (D4 + x * (D5 + x * (D6 +
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64CallingConvention.cpp | 33 AArch64::D3, AArch64::D4, AArch64::D5,
|
| H A D | AArch64PBQPRegAlloc.cpp | 65 case AArch64::D5:
|
| H A D | AArch64FastISel.cpp | 3016 AArch64::D5, AArch64::D6, AArch64::D7 },
|
| /freebsd-12-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | X86RecognizableInstr.h | 48 MAP(D5, 85) \
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 116 case AArch64::D5: return AArch64::B5;
156 case AArch64::B5: return AArch64::D5;
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 63 D0, D1, D2, D3, D4, D5, D6, D7, 0
|
| H A D | HexagonISelLowering.cpp | 280 .Case("r11:10", Hexagon::D5)
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 168 {codeview::RegisterId::ARM64_D5, AArch64::D5},
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 586 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 83 SP::D4, SP::D20, SP::D5, SP::D21,
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 150 Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 335 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9,
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1317 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 3236 case Mips::D5: return Mips::F11;
|
| /freebsd-12-stable/contrib/amd/doc/ |
| H A D | texinfo.tex | 9297 \DeclareUnicodeCharacter{00D5}{\~O}
|