| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstrInfo.h | 53 unsigned BaseOpcode; member in struct:llvm::AMDGPU::ImageDimIntrinsicInfo
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| H A D | SIISelLowering.cpp | 5340 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = local
5341 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode);
5344 AMDGPU::getMIMGLZMappingInfo(Intr->BaseOpcode);
5346 AMDGPU::getMIMGMIPMappingInfo(Intr->BaseOpcode);
5347 unsigned IntrOpcode = Intr->BaseOpcode;
5362 if (BaseOpcode->Atomic) {
5366 if (BaseOpcode->AtomicX2) {
5383 unsigned DMaskIdx = BaseOpcode->Store ? 3 : isa<MemSDNode>(Op) ? 2 : 1;
5386 DMaskLanes = BaseOpcode->Gather4 ? 4 : countPopulation(DMask);
5388 if (BaseOpcode
[all...] |
| H A D | SIShrinkInstructions.cpp | 293 AMDGPU::getMIMGOpcode(Info->BaseOpcode, AMDGPU::MIMGEncGfx10Default,
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| H A D | SIInstrInfo.cpp | 3658 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
3659 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
3669 unsigned AddrWords = BaseOpcode->NumExtraArgs +
3670 (BaseOpcode->Gradients ? Dim->NumGradients : 0) +
3671 (BaseOpcode->Coordinates ? Dim->NumCoords : 0) +
3672 (BaseOpcode->LodOrClampOrMip ? 1 : 0);
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| H A D | SILoadStoreOptimizer.cpp | 382 return Info->BaseOpcode;
425 if (Info && AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode)->Sampler)
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrFMA3Info.cpp | 135 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); local
140 ((BaseOpcode >= 0x96 && BaseOpcode <= 0x9F) ||
141 (BaseOpcode >= 0xA6 && BaseOpcode <= 0xAF) ||
142 (BaseOpcode >= 0xB6 && BaseOpcode <= 0xBF));
159 unsigned FormIndex = ((BaseOpcode - 0x90) >> 4) & 0x3;
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCCodeEmitter.cpp | 1408 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); local
1411 BaseOpcode = 0x0F; // Weird 3DNow! encoding.
1425 emitByte(BaseOpcode, CurByte, OS);
1434 emitByte(BaseOpcode + OpcodeOffset, CurByte, OS);
1446 emitByte(BaseOpcode, CurByte, OS);
1453 emitByte(BaseOpcode, CurByte, OS);
1461 emitByte(BaseOpcode, CurByte, OS);
1470 emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
1474 emitByte(BaseOpcode, CurByte, OS);
1489 emitByte(BaseOpcode, CurByt
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.h | 205 MIMGBaseOpcode BaseOpcode; member in struct:llvm::AMDGPU::MIMGBaseOpcodeInfo
220 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
257 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
265 uint16_t BaseOpcode; member in struct:llvm::AMDGPU::MIMGInfo
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| H A D | AMDGPUBaseInfo.cpp | 113 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, argument
115 const MIMGInfo *Info = getMIMGOpcodeHelper(BaseOpcode, MIMGEncoding,
122 return Info ? getMIMGBaseOpcodeInfo(Info->BaseOpcode) : nullptr;
128 getMIMGOpcodeHelper(OrigInfo->BaseOpcode, OrigInfo->MIMGEncoding,
135 uint16_t BaseOpcode; member in struct:llvm::AMDGPU::MUBUFInfo
144 uint16_t BaseOpcode; member in struct:llvm::AMDGPU::MTBUFInfo
159 return Info ? Info->BaseOpcode : -1;
189 return Info ? Info->BaseOpcode : -1;
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 494 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = local
495 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
499 AddrSize = BaseOpcode->NumExtraArgs +
500 (BaseOpcode->Gradients ? Dim->NumGradients : 0) +
501 (BaseOpcode->Coordinates ? Dim->NumCoords : 0) +
502 (BaseOpcode->LodOrClampOrMip ? 1 : 0);
534 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize);
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 7612 unsigned BaseOpcode = 0;
7615 case ISD::VECREDUCE_FADD: BaseOpcode = ISD::FADD; break;
7616 case ISD::VECREDUCE_FMUL: BaseOpcode = ISD::FMUL; break;
7617 case ISD::VECREDUCE_ADD: BaseOpcode = ISD::ADD; break;
7618 case ISD::VECREDUCE_MUL: BaseOpcode = ISD::MUL; break;
7619 case ISD::VECREDUCE_AND: BaseOpcode = ISD::AND; break;
7620 case ISD::VECREDUCE_OR: BaseOpcode = ISD::OR; break;
7621 case ISD::VECREDUCE_XOR: BaseOpcode = ISD::XOR; break;
7622 case ISD::VECREDUCE_SMAX: BaseOpcode = ISD::SMAX; break;
7623 case ISD::VECREDUCE_SMIN: BaseOpcode
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 2982 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = local
2983 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
3000 unsigned AddrSize = BaseOpcode->NumExtraArgs +
3001 (BaseOpcode->Gradients ? DimInfo->NumGradients : 0) +
3002 (BaseOpcode->Coordinates ? DimInfo->NumCoords : 0) +
3003 (BaseOpcode->LodOrClampOrMip ? 1 : 0);
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