Searched refs:BaseOpc (Results 1 - 5 of 5) sorted by relevance
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
H A D | AMDGPUBaseInfo.h | 278 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements); 296 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
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H A D | AMDGPUBaseInfo.cpp | 162 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements) { argument 163 const MTBUFInfo *Info = getMTBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements); 192 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements) { argument 193 const MUBUFInfo *Info = getMUBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMLoadStoreOptimizer.cpp | 699 int BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2ADDspImm local 711 BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2SUBspImm 734 (BaseOpc == ARM::tADDi8 || BaseOpc == ARM::tSUBi8)) { 752 if (BaseOpc == ARM::tADDrSPi) { 754 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) 759 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) 765 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 2889 unsigned BaseOpc, CondCode; local 2893 BaseOpc = ISD::ADD; CondCode = X86::COND_O; break; 2895 BaseOpc = ISD::ADD; CondCode = X86::COND_B; break; 2897 BaseOpc = ISD::SUB; CondCode = X86::COND_O; break; 2899 BaseOpc = ISD::SUB; CondCode = X86::COND_B; break; 2901 BaseOpc = X86ISD::SMUL; CondCode = X86::COND_O; break; 2903 BaseOpc = X86ISD::UMUL; CondCode = X86::COND_O; break; 2919 if (CI->isOne() && (BaseOpc == ISD::ADD || BaseOpc == ISD::SUB) && 2923 bool IsDec = BaseOpc [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 2763 unsigned BaseOpc = BO.first.getOpcode(); local 2764 if (BaseOpc == HexagonISD::VALIGNADDR && BO.second % LoadLen == 0) 2772 SDValue BaseNoOff = (BaseOpc != HexagonISD::VALIGNADDR)
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