Searched refs:AR_PHY_MC_GAIN_CTRL (Results 1 - 4 of 4) sorted by relevance
/freebsd-12-stable/sys/contrib/dev/ath/ath_hal/ar9300/ |
H A D | ar9300_eeprom.c | 1743 regval = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1768 OS_REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, 1778 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 1798 regval = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1808 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 1816 u_int32_t reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1831 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, reg_val); 1843 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, reg_val);
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H A D | ar9300_reset.c | 6484 regval = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 6494 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 6509 regval = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 6519 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 6527 OS_REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, ANT_DIV_ENABLE); 6528 OS_REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, (1 << MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__SHIFT)); 6533 OS_REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, ANT_DIV_ENABLE); 6534 OS_REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, (1 << MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__SHIFT)); 6539 regval = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 6549 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regva [all...] |
H A D | ar9300_attach.c | 4042 u_int32_t reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 4075 reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 4096 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, reg_val);
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H A D | ar9300phy.h | 349 #define AR_PHY_MC_GAIN_CTRL AR_AGC_OFFSET(BB_multichain_gain_ctrl) macro
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