| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsAnalyzeImmediate.cpp | 35 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL));
59 // A single ADDiu will do if RemSize <= 16.
61 AddInstr(SeqLs, Inst(ADDiu, MaskedImm));
74 // instruction is an ADDiu or ORi. In that case, do not call GetInstSeqLsORi.
83 // Replace a ADDiu & SLL pair with a LUi.
85 // ADDiu 0x0111
90 // Check if the first two instructions are ADDiu and SLL and the shift amount
92 if ((Seq.size() < 2) || (Seq[0].Opc != ADDiu) ||
96 // Sign-extend and shift operand of ADDiu and see if it still fits in 16-bit.
134 ADDiu
[all...] |
| H A D | MipsAnalyzeImmediate.h | 27 /// instruction in the sequence must be an ADDiu if LastInstrIsADDiu is
37 /// GetInstSeqLsADDiu - Get instruction sequences which end with an ADDiu to
52 /// ReplaceADDiuSLLWithLUi - Replace an ADDiu & SLL pair with a LUi.
60 unsigned ADDiu, ORi, SLL, LUi; member in class:llvm::MipsAnalyzeImmediate
|
| H A D | MipsInstructionSelector.cpp | 154 // ADDiu sign extends immediate. Used for values with 1s in high 17 bits.
157 B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)})
319 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
593 MachineInstr *ADDiu = local
594 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
598 ADDiu->getOperand(2).setTargetFlags(MipsII::MO_ABS_LO);
599 if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI))
612 MachineInstr *ADDiu =
613 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
617 ADDiu
[all...] |
| H A D | MipsMachineFunction.cpp | 104 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
120 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
|
| H A D | MipsBranchExpansion.cpp | 456 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
464 // LUi and ADDiu instructions create 32-bit offset of the target basic
473 // we replace LUi and ADDiu with pseudo instructions
476 // instructions to LUi and ADDiu in the MC layer, we will create
517 BuildMI(*BalTgtMBB, std::prev(Pos), DL, TII->get(Mips::ADDiu), Mips::SP)
525 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
726 BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0)
|
| H A D | MipsMCInstLower.cpp | 306 lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu);
|
| H A D | MipsSEISelDAGToDAG.cpp | 88 if ((MI.getOpcode() == Mips::ADDiu) &&
146 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::ADDiu))
813 // instructions (ADDiu, ORI and SLL) in that it does not have a register
1040 const unsigned ADDiuOp = Is32BitSplat ? Mips::ADDiu : Mips::DADDiu;
|
| H A D | MicroMipsSizeReduction.cpp | 214 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUR1SP_MM),
216 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUSP_MM), ReduceADDIUToADDIUSP,
|
| H A D | MipsFastISel.cpp | 369 unsigned Opc = Mips::ADDiu;
428 emitInst(Mips::ADDiu, TempReg)
743 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
744 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
|
| H A D | MipsSEFrameLowering.cpp | 418 unsigned ADDiu = ABI.GetPtrAddiuOp(); local
546 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO) .addImm(MaxAlign);
|
| H A D | MipsSEInstrInfo.cpp | 580 unsigned ADDiu = ABI.GetPtrAddiuOp(); local
587 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
624 // instructions (ADDiu, ORI and SLL) in that it does not have a register
|
| H A D | MipsAsmPrinter.cpp | 1230 MCInstBuilder(Mips::ADDiu)
|
| H A D | MipsSEISelLowering.cpp | 3069 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
3075 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
3138 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
3144 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
|
| H A D | MipsISelLowering.cpp | 1968 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsABIInfo.cpp | 103 return ArePtrs64bit() ? Mips::DADDiu : Mips::ADDiu;
|
| H A D | MipsTargetStreamer.cpp | 1146 TmpInst.setOpcode(Mips::ADDiu);
1229 emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(),
1246 emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(),
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 2528 case Mips::ADDiu: case Mips::ADDiu_MM:
2723 TOut.emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI);
2973 TOut.emitRRX(IsPtr64 ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg,
3040 TOut.emitRRX(IsPtr64 ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg,
3179 TOut.emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr),
3453 TOut.emitRRX(isABI_N64() ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg, member in class:Mips
4274 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI);
4285 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, STI);
4675 case Mips::ADDiu:
5304 Opc = isGP64bit() ? Mips::DADDiu : Mips::ADDiu;
[all...] |