Searched refs:_i (Results 1 - 25 of 56) sorted by relevance

123

/freebsd-12-stable/contrib/gcc/config/soft-fp/
H A Dop-8.h42 _FP_I_TYPE _up, _down, _skip, _i; \
47 for (_i = 7; _i >= _skip; --_i) \
48 X##_f[_i] = X##_f[_i-_skip]; \
51 for (_i = 7; _i > _skip; --_i) \
52 X##_f[_i]
[all...]
H A Dop-4.h45 _FP_I_TYPE _up, _down, _skip, _i; \
50 for (_i = 3; _i >= _skip; --_i) \
51 X##_f[_i] = X##_f[_i-_skip]; \
54 for (_i = 3; _i > _skip; --_i) \
55 X##_f[_i]
[all...]
/freebsd-12-stable/sys/sys/
H A Dcounter.h46 for (int _i = 0; _i < (n); _i++) \
47 (a)[_i] = counter_u64_alloc(wait); \
51 for (int _i = 0; _i < (n); _i++) \
52 counter_u64_free((a)[_i]); \
56 for (int _i = 0; _i < (
[all...]
H A Dpcpu.h137 u_int _i; \
141 CPU_FOREACH(_i) { \
142 sum += *DPCPU_ID_PTR(_i, n); \
149 u_int _i; \
153 CPU_FOREACH(_i) { \
154 sum += (DPCPU_ID_PTR(_i, n))->var; \
160 u_int _i; \
162 CPU_FOREACH(_i) { \
163 bzero(DPCPU_ID_PTR(_i, n), sizeof(*DPCPU_PTR(n))); \
/freebsd-12-stable/sys/dev/ixl/
H A Di40e_register.h120 #define I40E_VF_ARQBAH(_VF) (0x00081400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
124 #define I40E_VF_ARQBAL(_VF) (0x00080C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
128 #define I40E_VF_ARQH(_VF) (0x00082400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
132 #define I40E_VF_ARQLEN(_VF) (0x00081C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
144 #define I40E_VF_ARQT(_VF) (0x00082C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
148 #define I40E_VF_ATQBAH(_VF) (0x00081000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
152 #define I40E_VF_ATQBAL(_VF) (0x00080800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
156 #define I40E_VF_ATQH(_VF) (0x00082000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
160 #define I40E_VF_ATQLEN(_VF) (0x00081800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
172 #define I40E_VF_ATQT(_VF) (0x00082800 + ((_VF) * 4)) /* _i
[all...]
/freebsd-12-stable/sys/dev/ice/
H A Dice_hw_autogen.h54 #define MSIX_PBA(_i) (0x00008000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: FLR */
58 #define MSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */
64 #define MSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */
68 #define MSIX_TVCTRL(_i) (
[all...]
H A Dice_nvm.h88 #define GL_HIDA(_i) (0x00082000 + ((_i) * 4))
89 #define GL_HIBA(_i) (0x00081000 + ((_i) * 4))
/freebsd-12-stable/sys/contrib/ngatm/netnatm/sig/
H A Dunimkmsg.h113 u_int _i, _j; \
115 for(_i = _j = 0; _i < 2; _i++) \
116 if(IE_ISGOOD((U)->u.release_compl.cause[_i])) \
118 (U)->u.release_compl.cause[_i]; \
119 for(_i = _j = 0; _i < UNI_NUM_IE_GIT; _i++) \
120 if(IE_ISGOOD((U)->u.release_compl.git[_i])) \
[all...]
/freebsd-12-stable/sys/dev/ixgbe/
H A Dixgbe_type.h336 #define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
337 #define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
338 #define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
339 #define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
349 #define IXGBE_EITR(_i) (((_i) <
[all...]
/freebsd-12-stable/sys/dev/virtio/
H A Dvirtqueue.h61 #define VQ_ALLOC_INFO_INIT(_i,_nsegs,_intr,_arg,_vqp,_str,...) do { \
62 snprintf((_i)->vqai_name, VIRTQUEUE_MAX_NAME_SZ, _str, \
64 (_i)->vqai_maxindirsz = (_nsegs); \
65 (_i)->vqai_intr = (_intr); \
66 (_i)->vqai_intr_arg = (_arg); \
67 (_i)->vqai_vq = (_vqp); \
/freebsd-12-stable/sys/mips/broadcom/
H A Dbcm_mips74kreg.h53 #define BCM_MIPS74K_INTR_SEL_FLAG(_i) (1<<_i)
/freebsd-12-stable/sys/dev/e1000/
H A De1000_ich8lan.h77 #define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8))
78 #define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8))
151 #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
152 #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
153 #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) <<
[all...]
H A De1000_regs.h279 #define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4))
280 #define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
281 (0x054E0 + ((_i - 16) * 8)))
282 #define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
283 (0x054E4 + ((_i
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/freebsd-12-stable/libexec/rc/rc.d/
H A Dmdconfig67 local _i
90 for _i in `df ${_file} 2>/dev/null`; do _fs=${_i}; done
157 local _md _mp _config _type _dev _file _fs _newfs _i
162 for _i in `df ${_dev} 2>/dev/null`; do _mp=${_i}; done
H A Dmdconfig268 local _i
96 for _i in `df ${_file} 2>/dev/null`; do _fs=${_i}; done
113 local _md _fs _mp _mounted _dev _config _type _file _owner _perms _files _populate _fsck_cmd _i
158 for _i in `df ${_dev} 2>/dev/null`; do _mp=${_i}; done
H A Djail283 local _i _interface
284 _i=$1
287 if [ -z "${_i}" ]; then
294 case "${_i}" in
296 _iface=${_i%%|*}
297 _r=${_i##*|}
300 _r=${_i}
353 local _x _type _i _defif
368 _i=`expr -- "${_x}" : '^\([^,]*\)'`
371 *) _i
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/freebsd-12-stable/sys/dev/ath/ath_hal/ar5416/
H A Dar5416phy.h147 #define AR_PHY_TIMING_CTRL4_CHAIN(_i) \
148 (AR_PHY_TIMING_CTRL4 + ((_i) << 12))
221 #define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12))
222 #define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12))
223 #define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12))
225 #define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 1
[all...]
/freebsd-12-stable/sys/dev/etherswitch/arswitch/
H A Darswitchreg.h486 #define AR8327_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
489 #define AR8327_REG_PORT_HEADER(_i) (0x09c + (_i) * 4)
497 #define AR8327_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2)
499 #define AR8327_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8)
505 #define AR8327_REG_PORT_VLAN1(_i) (0x424 + (_i) *
[all...]
/freebsd-12-stable/sys/dev/bhnd/tools/
H A Dnvram_map_gen.awk45 function main(_i) {
74 for (_i = 1; _i < ARGC; _i++) {
75 if (ARGV[_i] == "--debug") {
77 } else if (ARGV[_i] == "-d" && OUT_T == null) {
79 } else if (ARGV[_i] == "-h" && OUT_T == null) {
81 } else if (ARGV[_i] == "-v") {
83 } else if (ARGV[_i] == "-o") {
84 _i
[all...]
/freebsd-12-stable/sys/cddl/contrib/opensolaris/uts/common/sys/
H A Dcpuvar.h471 int _i; \
472 for (_i = 0; _i < CPUSET_WORDS; _i++) \
473 (set1).cpub[_i] |= (set2).cpub[_i]; \
477 int _i; \
478 for (_i = 0; _i < CPUSET_WORDS; _i
[all...]
/freebsd-12-stable/sys/dev/bhnd/siba/
H A Dsibareg.h125 #define SIBA_IPS_INT_SHIFT(_i) ((_i - 1) * 8)
126 #define SIBA_IPS_INT_MASK(_i) (SIBA_IPS_INT1_MASK << SIBA_IPS_INT_SHIFT(_i))
/freebsd-12-stable/sbin/pfctl/
H A Dpfctl_osfp.c559 int _dot = -1, _start = -1, _end = -1, _i = 0; \
561 if (isdigit(fp->field[_i]) && fp->field[_i+1] == '.') { \
562 _dot = fp->field[_i] - '0'; \
563 _i += 2; \
565 if (isdigit(fp->field[_i])) \
566 _start = fp->field[_i++] - '0'; \
569 if (isdigit(fp->field[_i])) \
570 _start = (_start * 10) + fp->field[_i++] - '0'; \
571 if (fp->field[_i
[all...]
/freebsd-12-stable/sys/dev/ath/ath_hal/ar5212/
H A Dar5212reg.h96 #define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2))
113 #define AR_QCBRCFG(_i) (AR_Q0_CBRCFG + ((_i)<<2))
125 #define AR_QRDYTIMECFG(_i) (AR_Q0_RDYTIMECFG + ((_i)<<2))
140 #define AR_QMISC(_i) (AR_Q0_MISC + ((_i)<<2))
152 #define AR_QSTS(_i) (AR_Q0_STS + ((_i)<<
[all...]
/freebsd-12-stable/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300phy.h331 #define AR_PHY_BBB_RX_CTRL(_i) AR_BBB_OFFSET(BB_bbb_rx_ctrl_##_i)
549 #define AR_PHY_RF_CTL(_i) AR_SM_OFFSET(BB_tx_timing_##_i)
773 #define AR_PHY_TX_FIR(_i) AR_SM_OFFSET(BB_bbb_txfir_##_i)
780 #define AR_PHY_POWER_TX_RATE(_i) AR_SM_OFFSET(BB_powertx_rate##_i)
790 #define AR_PHY_TPC(_i) AR_SM_OFFSET(BB_tpc_##_i) /* value
[all...]
/freebsd-12-stable/sys/mips/mediatek/
H A Dmtk_intr_gic.c68 #define MTK_MAPPIN(_i) (0x0500 + (4 * (_i)))
69 #define MTK_MAPVPE(_i, _v) (0x2000 + (32 * (_i)) + (((_v) / 32) * 4))
75 #define MTK_PIN_BITS(_i) ((1 << 31) | (_i))

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