Searched refs:train_set (Results 1 - 3 of 3) sorted by relevance

/freebsd-11.0-release/sys/dev/drm2/radeon/
H A Datombios_dp.c300 u8 train_set[4])
332 train_set[lane] = v | p;
582 u8 train_set[4]; member in struct:radeon_dp_link_train_info
593 0, dp_info->train_set[0]); /* sets all lanes at once */
597 dp_info->train_set, dp_info->dp_lane_count, 0);
713 memset(dp_info->train_set, 0, 4);
736 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
744 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
753 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
755 /* Compute new train_set a
298 dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], int lane_count, u8 train_set[4]) argument
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/freebsd-11.0-release/sys/dev/drm2/i915/
H A Dintel_dp.c1544 intel_dp->train_set[lane] = v | p;
1548 intel_dp_signal_levels(uint8_t train_set) argument
1552 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1567 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1587 intel_gen6_edp_signal_levels(uint8_t train_set) argument
1589 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1615 intel_gen7_edp_signal_levels(uint8_t train_set) argument
1617 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1646 intel_dp_signal_levels_hsw(uint8_t train_set) argument
1648 int signal_levels = train_set
[all...]
H A Dintel_drv.h392 uint8_t train_set[4]; member in struct:intel_dp

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