Searched refs:post_qid (Results 1 - 11 of 11) sorted by relevance

/freebsd-11.0-release/sys/dev/nxge/xgehal/
H A Dxgehal-channel-fp.c54 channel->type, channel->post_qid,
86 "free_length %d", channel->type, channel->post_qid,
106 channel->type, channel->post_qid,
130 channel->post_qid, channel->compl_qid, offset,
137 channel->type, channel->post_qid, channel->compl_qid,
191 channel->type, channel->post_qid,
243 return channel->post_qid;
H A Dxgehal-channel.c99 __hal_channel_allocate(xge_hal_device_h devh, int post_qid, argument
108 xge_assert(post_qid + 1 >= XGE_HAL_MIN_FIFO_NUM &&
109 post_qid + 1 <= XGE_HAL_MAX_FIFO_NUM);
113 xge_assert(post_qid + 1 >= XGE_HAL_MIN_RING_NUM &&
114 post_qid + 1 <= XGE_HAL_MAX_RING_NUM);
136 channel->post_qid = post_qid;
320 tmp->post_qid == attr->post_qid &&
H A Dxgehal-ring.c258 queue = &ring->config->queue[attr->post_qid];
360 queue = &ring->config->queue[ring->channel.post_qid];
403 queue = &ring->config->queue[ring->channel.post_qid];
416 val64, &bar0->prc_rxd0_n[ring->channel.post_qid]);
419 ring->channel.post_qid, (unsigned long long)val64);
422 ring->channel.regh0, &bar0->prc_ctrl_n[ring->channel.post_qid]);
446 val64, &bar0->prc_ctrl_n[ring->channel.post_qid]);
461 ring->channel.post_qid, queue->buffer_mode);
478 &bar0->prc_ctrl_n[ring->channel.post_qid]);
481 val64, &bar0->prc_ctrl_n[ring->channel.post_qid]);
[all...]
H A Dxgehal-device-fp.c120 (fifo->channel.post_qid * XGE_HAL_FIFO_HW_PAIR_OFFSET));
371 hldev->irq_workload_rxd[channel->post_qid] += *got_rx;
372 hldev->irq_workload_rxcnt[channel->post_qid] ++;
374 hldev->irq_workload_rxlen[channel->post_qid] += got_bytes;
418 hldev->irq_workload_txd[channel->post_qid] += *got_tx;
419 hldev->irq_workload_txcnt[channel->post_qid] ++;
421 hldev->irq_workload_txlen[channel->post_qid] += got_bytes;
H A Dxgehal-fifo.c166 queue = &fifo->config->queue[attr->post_qid];
198 (attr->post_qid * XGE_HAL_FIFO_HW_PAIR_OFFSET));
476 tmp->post_qid == i) {
H A Dxgehal-ring-fp.c495 xge_debug_ring(XGE_TRACE, "xge_hal_ring_dtr_pre_post: rxd 0x"XGE_OS_LLXFMT" posted %d post_qid %d",
498 ((xge_hal_ring_t *)channelh)->channel.post_qid);
729 "compl_index %d post_qid %d t_code %d rxd 0x"XGE_OS_LLXFMT,
731 ((xge_hal_channel_t*)ring)->post_qid, *t_code,
H A Dxgehal-mgmtaux.c965 (void) xge_os_sprintf(key, "ring%d_", channel->post_qid);
996 (void) xge_os_sprintf(key, "fifo%d_", channel->post_qid);
1260 (void) xge_os_sprintf(key, "ring%d_", channel->post_qid);
1297 (void) xge_os_sprintf(key, "fifo%d_", channel->post_qid);
H A Dxgehal-device.c6445 * @ring: The post_qid of the ring.
6471 * @ring: The post_qid of the FIFO.
6516 int ring = channel->post_qid;
6526 int fifo = channel->post_qid;
6663 int ring = channel->post_qid;
6670 hldev->config.fifo.queue[channel->post_qid].intr_vector =
6673 int fifo = channel->post_qid;
6680 hldev->config.ring.queue[channel->post_qid].intr_vector =
H A Dxgehal-mgmt.c532 __hal_update_ring_bump( (xge_hal_device_t *) channel->devh, channel->post_qid, channel_info);
/freebsd-11.0-release/sys/dev/nxge/include/
H A Dxgehal-channel.h225 * @post_qid: Queue ID to post descriptors. For the link layer this
253 int post_qid; member in struct:xge_hal_channel_attr_t
324 * @post_qid: Identifies Xframe queue used for posting descriptors.
389 int post_qid; member in struct:__anon11194
425 __hal_channel_allocate(xge_hal_device_h devh, int post_qid,
/freebsd-11.0-release/sys/dev/nxge/
H A Dif_nxge.c1922 .post_qid = qid,
1983 attr.post_qid = qindex,

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