Searched refs:pbl_size (Results 1 - 7 of 7) sorted by relevance

/freebsd-11.0-release/sys/dev/cxgbe/iw_cxgbe/
H A Dmem.c131 * pbl_size and pbl_addr
138 u64 len, u8 page_size, u32 pbl_size, u32 pbl_addr)
183 tpt.nosnoop_pbladdr = !pbl_size ? 0 : cpu_to_be32(
205 u32 pbl_addr, u32 pbl_size)
209 CTR4(KTR_IW_CXGBE, "%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d",
210 __func__, pbl_addr, rdev->adap->vres.pbl.start, pbl_size);
212 err = write_adapter_mem(rdev, pbl_addr >> 5, pbl_size << 3, pbl);
216 static int dereg_mem(struct c4iw_rdev *rdev, u32 stag, u32 pbl_size, argument
220 pbl_size, pbl_addr);
237 u32 pbl_size, u3
134 write_tpt_entry(struct c4iw_rdev *rdev, u32 reset_tpt_entry, u32 *stag, u8 stag_state, u32 pdid, enum fw_ri_stag_type type, enum fw_ri_mem_perms perm, int bind_enabled, u32 zbva, u64 to, u64 len, u8 page_size, u32 pbl_size, u32 pbl_addr) argument
204 write_pbl(struct c4iw_rdev *rdev, __be64 *pbl, u32 pbl_addr, u32 pbl_size) argument
236 allocate_stag(struct c4iw_rdev *rdev, u32 *stag, u32 pdid, u32 pbl_size, u32 pbl_addr) argument
[all...]
H A Diw_cxgbe.h326 u32 pbl_size; member in struct:tpt_attributes
/freebsd-11.0-release/sys/dev/cxgb/ulp/iw_cxgb/
H A Diw_cxgb_mem.c105 mhp->attr.pbl_size, mhp->attr.pbl_addr))
110 cxio_dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
124 if (npages > mhp->attr.pbl_size)
135 mhp->attr.pbl_size, mhp->attr.pbl_addr))
140 cxio_dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
153 mhp->attr.pbl_size = npages;
161 mhp->attr.pbl_size << 3);
232 CTR6(KTR_IW_CXGB, "%s va 0x%llx mask 0x%llx shift %d len %lld pbl_size %d",
H A Diw_cxgb_hal.h150 u32 pbl_addr, u32 pbl_size);
153 u8 page_size, u32 pbl_size, u32 pbl_addr);
156 u8 page_size, u32 pbl_size, u32 pbl_addr);
157 int cxio_dereg_mem(struct cxio_rdev *rdev, u32 stag, u32 pbl_size,
H A Diw_cxgb_hal.c729 /* IN: stag key, pdid, perm, zbva, to, len, page_size, pbl, and pbl_size
730 * OUT: stag index, actual pbl_size, pbl_addr allocated.
738 u32 pbl_size, u32 pbl_addr)
779 htobe32(V_TPT_PBL_SIZE((pbl_size) >> 2));
801 u32 pbl_addr, u32 pbl_size)
806 CTR4(KTR_IW_CXGB, "%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d",
808 pbl_size);
811 err = cxio_hal_ctrl_qp_write_mem(rdev_p, pbl_addr >> 5, pbl_size << 3,
829 u8 page_size, u32 pbl_size, u32 pbl_addr)
833 zbva, to, len, page_size, pbl_size, pbl_add
734 __cxio_tpt_op(struct cxio_rdev *rdev_p, u32 reset_tpt_entry, u32 *stag, u8 stag_state, u32 pdid, enum tpt_mem_type type, enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len, u8 page_size, u32 pbl_size, u32 pbl_addr) argument
800 cxio_write_pbl(struct cxio_rdev *rdev_p, __be64 *pbl, u32 pbl_addr, u32 pbl_size) argument
827 cxio_register_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid, enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len, u8 page_size, u32 pbl_size, u32 pbl_addr) argument
837 cxio_reregister_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid, enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len, u8 page_size, u32 pbl_size, u32 pbl_addr) argument
846 cxio_dereg_mem(struct cxio_rdev *rdev_p, u32 stag, u32 pbl_size, u32 pbl_addr) argument
[all...]
H A Diw_cxgb_provider.h67 u32 pbl_size; member in struct:tpt_attributes
H A Diw_cxgb_provider.c387 cxio_dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
461 mhp->attr.pbl_size = npages;
537 mhp->attr.pbl_size = npages;

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