Searched refs:instructions (Results 1 - 25 of 56) sorted by relevance

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/freebsd-11.0-release/contrib/binutils/opcodes/
H A Darc-ext.h48 struct ExtInstruction *instructions[NUM_EXT_INST]; member in struct:arcExtMap
H A Darc-ext.c49 if (!arc_extension_map.instructions[opcode])
51 *flags = arc_extension_map.instructions[opcode]->flags;
52 return arc_extension_map.instructions[opcode]->name;
124 /* clean instructions */
127 insn = arc_extension_map.instructions[i];
160 For instructions:
193 arc_extension_map.instructions[(int) opcode] = insn;
/freebsd-11.0-release/contrib/llvm/lib/Transforms/Scalar/
H A DADCE.cpp11 // optimistically assumes that all instructions are dead until proven otherwise,
34 STATISTIC(NumRemoved, "Number of instructions removed");
40 // Collect the set of "root" instructions that are known live.
41 for (Instruction &I : instructions(F)) {
59 // The inverse of the live set is the dead set. These are those instructions
63 for (Instruction &I : instructions(F)) {
H A DBDCE.cpp11 // instructions (shifts, some ands, ors, etc.) kill some of their input bits.
12 // We track these dead bits and remove instructions that compute only these
34 STATISTIC(NumRemoved, "Number of instructions removed (unused)");
35 STATISTIC(NumSimplified, "Number of instructions trivialized (dead bits)");
68 for (Instruction &I : instructions(F)) {
71 // For live instructions that have all dead bits, first make them dead by
/freebsd-11.0-release/contrib/subversion/subversion/libsvn_fs_x/
H A Dreps.c49 /* Limit the size of the instructions stream. This should not exceed the
56 /* Byte strings are described by a series of copy instructions that each
61 * - reference other instruction and specify how many of instructions of
68 * instruction and the number of instructions to execute.
83 * container->instructions[-offset].
93 /* Number of bytes to copy / instructions to execute
112 * instructions for this base. */
174 /* array of instruction_t objects describing all instructions */
175 apr_array_header_t *instructions; member in struct:svn_fs_x__reps_builder_t
197 /* fulltext i can be reconstructed by executing instructions
207 const instruction_t *instructions; member in struct:svn_fs_x__reps_t
777 instruction_t *instructions; local
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/freebsd-11.0-release/contrib/llvm/include/llvm/IR/
H A DInstIterator.h11 // instructions in a function. This is effectively a wrapper around a two level
15 // instructions are moved around.
128 inline inst_range instructions(Function *F) { function in namespace:llvm
137 inline const_inst_range instructions(const Function *F) { function in namespace:llvm
142 inline inst_range instructions(Function &F) { function in namespace:llvm
151 inline const_inst_range instructions(const Function &F) { function in namespace:llvm
/freebsd-11.0-release/usr.bin/bc/
H A Dbc.y100 static struct tree *instructions = NULL;
774 p = realloc(instructions, newsize * sizeof(*p));
776 free(instructions);
779 instructions = p;
789 instructions[current].index = CONST_STRING;
790 instructions[current].u.cstr = str;
799 instructions[current].index = ALLOC_STRING;
800 instructions[current].u.astr = strdup(str);
801 if (instructions[current].u.astr == NULL)
816 instructions[curren
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/freebsd-11.0-release/contrib/llvm/lib/Analysis/
H A DMemDerefPrinter.cpp56 for (auto &I: instructions(F)) {
H A DMemDepPrinter.cpp99 for (auto &I : instructions(F)) {
138 for (const auto &I : instructions(*F)) {
H A DDivergenceAnalysis.cpp118 for (auto &I : instructions(F)) {
307 llvm_unreachable("Only arguments and instructions can be divergent");
310 // Dumps all divergent values in F, arguments and then instructions.
315 // Iterate instructions using instructions() to ensure a deterministic order.
316 for (auto &I : instructions(F)) {
/freebsd-11.0-release/contrib/llvm/tools/lldb/source/Target/
H A DThreadPlanStepRange.cpp70 // FIXME: The DisassemblerLLVMC has a reference cycle and won't go away if it has any active instructions.
368 InstructionList *instructions = GetInstructionsForAddress (cur_addr, range_index, pc_index); local
369 if (instructions == nullptr)
375 branch_index = instructions->GetIndexOfNextBranchInstruction (pc_index, target);
382 uint32_t last_index = instructions->GetSize() - 1;
385 InstructionSP last_inst = instructions->GetInstructionAtIndex(last_index);
393 run_to_address = instructions->GetInstructionAtIndex(branch_index)->GetAddress();
/freebsd-11.0-release/contrib/subversion/subversion/libsvn_delta/
H A Dsvndiff.c54 /* This is at least as big as the largest possible instructions
55 section: in theory, the instructions could be SVN_DELTA_WINDOW_SIZE
56 1-byte copy-from-source instructions (though this is very unlikely). */
124 /* append instructions (1 to a handful of bytes) */
143 svn_stringbuf_t *instructions; local
188 instructions = svn_stringbuf_create_empty(pool);
192 /* Encode the instructions. */
209 svn_stringbuf_appendbytes(instructions, (const char *)ibuf, ip - ibuf);
218 SVN_ERR(svn__compress(instructions, i1, eb->compression_level));
219 instructions
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/freebsd-11.0-release/contrib/llvm/lib/CodeGen/
H A DInterleavedAccessPass.cpp20 // can be easily matched into target specific instructions later in CodeGen.
270 // Holds dead instructions that will be erased later.
274 for (auto &I : instructions(F)) {
/freebsd-11.0-release/contrib/llvm/lib/Support/Unix/
H A DMemory.inc60 // Cache uses instructions dcbf and icbi, both of which are treated by
62 // executing these instructions will result in a segmentation fault.
/freebsd-11.0-release/contrib/llvm/utils/TableGen/
H A DCodeGenTarget.h164 /// getInstructionsByEnumValue - Return all of the instructions defined by the
175 iterator_range<inst_iterator> instructions() const { function in class:llvm::CodeGenTarget
185 /// encodings, reverse the bit order of all instructions.
H A DInstrInfoEmitter.cpp180 for (const CodeGenInstruction *Inst : Target.instructions()) {
198 /// each instructions. This is used to generate the OperandMap table as
361 for (const CodeGenInstruction *II : Target.instructions()) {
564 // emitEnums - Print out enum values for all of the instructions.
578 PrintFatalError("No instructions defined!");
/freebsd-11.0-release/contrib/gcc/config/rs6000/
H A Ddarwin-vecsave.asm36 save/restore requires 2 instructions (8 bytes.)
41 (4 bytes) to do the operation; for Vector regs, 2 instructions are
H A Ddarwin-fpsave.asm38 (4 bytes) to do the operation; for Vector regs, 2 instructions are
H A Ddarwin-tramp.asm81 /* Copy the instructions to the stack */
/freebsd-11.0-release/contrib/gcc/config/ia64/
H A Dcrti.asm35 # .init sections. Users may put any desired instructions in those
H A Dcrtend.asm56 * the long branch instructions, and we do not wish every program to
/freebsd-11.0-release/contrib/gcc/config/arm/
H A Dcrti.asm35 # .init sections. Users may put any desired instructions in those
/freebsd-11.0-release/contrib/gcc/config/sparc/
H A Dsol2-ci.asm37 ! .init sections. Users may put any desired instructions in those
/freebsd-11.0-release/contrib/llvm/projects/libunwind/src/
H A DUnwindRegistersRestore.S352 @ VFP and iwMMX instructions are only available when compiling with the flags
354 @ want the compiler to generate instructions that access those) but this is
H A DUnwindRegistersSave.S371 @ VFP and iwMMX instructions are only available when compiling with the flags
373 @ want the compiler to generate instructions that access those) but this is
377 @ So, generate the instructions using the corresponding coprocessor mnemonic.

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