Searched refs:Writes (Results 1 - 7 of 7) sorted by relevance
/freebsd-11.0-release/contrib/llvm/utils/TableGen/ |
H A D | CodeGenSchedule.h | 109 /// Writes and ReadDefs are empty. ProcIndices contains 0 for any processor. 118 /// provided InstrRW records for this class. ItinClassDef or Writes/Reads may 126 /// that mapped the itinerary class to the variant Writes or Reads. 132 IdxVec Writes; member in struct:llvm::CodeGenSchedClass 148 return ItinClassDef == IC && makeArrayRef(Writes) == W && 359 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const; 371 unsigned findSchedClassIdx(Record *ItinClassDef, ArrayRef<unsigned> Writes, 417 void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads,
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H A D | CodeGenSchedule.cpp | 180 RecVec Seq = RWDef->getValueAsListOfDefs("Writes"); 287 findRWs(WI->TheDef->getValueAsListOfDefs("Writes"), WI->Sequence, 377 IdxVec &Writes, IdxVec &Reads) const { 381 findRWs(WriteDefs, Writes, false); 503 IdxVec Writes, Reads; 505 findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads); 510 unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, ProcIndices); 544 if (!SC.Writes.empty()) { 547 for (IdxIter WI = SC.Writes.begin(), WE = SC.Writes [all...] |
H A D | SubtargetEmitter.cpp | 857 IdxVec Writes = SCI->Writes; local 872 Writes.clear(); 875 Writes, Reads); 878 if (Writes.empty()) { 886 Writes, Reads); 890 if (Writes.empty()) { 900 for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI) {
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/freebsd-11.0-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | MachineInstrBundle.h | 158 /// Writes - One of the operands writes the virtual register. 159 bool Writes; member in struct:llvm::MachineOperandIteratorBase::VirtRegInfo
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/freebsd-11.0-release/contrib/llvm/lib/CodeGen/ |
H A D | MachineInstrBundle.cpp | 285 RI.Writes = true;
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H A D | InlineSpiller.cpp | 1267 if (RI.Writes) { 1310 if (RI.Writes)
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H A D | RegisterCoalescer.cpp | 1183 bool Reads, Writes; local 1184 std::tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
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