Searched refs:TReg (Results 1 - 3 of 3) sorted by relevance
| /freebsd-11.0-release/contrib/llvm/lib/CodeGen/ |
| H A D | EarlyIfConversion.cpp | 112 unsigned TReg, FReg; member in struct:__anon2452::SSAIfConv::PHIInfo
113 // Latencies from Cond+Branch, TReg, and FReg to DstReg.
117 : PHI(phi), TReg(0), FReg(0), CondCycles(0), TCycles(0), FCycles(0) {}
415 PI.TReg = PI.PHI->getOperand(i).getReg();
419 assert(TargetRegisterInfo::isVirtualRegister(PI.TReg) && "Bad PHI");
423 if (!TII->canInsertSelect(*Head, Cond, PI.TReg, PI.FReg,
464 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg);
485 if (PI.TReg == PI.FReg) {
488 DstReg = PI.TReg;
493 DstReg, Cond, PI.TReg, P
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| /freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMAsmPrinter.cpp | 1312 unsigned TReg = MI->getOperand(0).getReg(); local
1315 if (ThumbIndirectPads[i].first == TReg) {
1323 ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
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| /freebsd-11.0-release/contrib/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 3243 unsigned TReg = Inst.getOperand(2).getReg(); local
3258 emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), Instructions);
3264 emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), Instructions);
3290 emitRRR(Mips::SUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), Instructions);
3292 emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), Instructions);
3371 unsigned TReg = Inst.getOperand(2).getReg(); local
3386 emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), Instructions);
3392 emitRRR(Mips::DROTRV, DReg, SReg, TReg, Inst.getLoc(), Instructions);
3418 emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), Instructions);
3420 emitRRR(SecondShift, DReg, SReg, TReg, Ins
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