Searched refs:Src0Reg (Results 1 - 9 of 9) sorted by relevance
/openbsd-current/gnu/llvm/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.h | 269 unsigned Src0Reg,
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H A D | AMDGPUInstructionSelector.cpp | 428 Register Src0Reg = I.getOperand(2).getReg(); local 449 !RBI.constrainGenericRegister(Src0Reg, AMDGPU::SReg_32RegClass, *MRI) || 835 Register Src0Reg = I.getOperand(1).getReg(); local 862 const RegisterBank *Src0Bank = RBI.getRegBank(Src0Reg, *MRI, TRI); 876 !RBI.constrainGenericRegister(Src0Reg, *Src0RC, *MRI) || 882 .addReg(Src0Reg) 1071 Register Src0Reg = I.getOperand(2).getReg(); local 1076 for (Register Reg : { DstReg, Src0Reg, Src1Reg }) 1352 Register Src0Reg = local 1358 .addReg(Src0Reg) [all...] |
H A D | R600InstrInfo.cpp | 1215 unsigned Src0Reg, 1228 .addReg(Src0Reg) // $src0
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H A D | AMDGPULegalizerInfo.cpp | 2100 Register Src0Reg = MI.getOperand(1).getReg(); 2105 auto Div = B.buildFDiv(Ty, Src0Reg, Src1Reg, Flags); 2108 B.buildFMA(DstReg, Neg, Src1Reg, Src0Reg, Flags);
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H A D | AMDGPURegisterBankInfo.cpp | 4322 Register Src0Reg = MI.getOperand(2).getReg(); 4324 unsigned Src0Size = MRI.getType(Src0Reg).getSizeInBits();
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H A D | SIInstrInfo.cpp | 5280 Register Src0Reg = Src0.getReg(); 5292 Src1.ChangeToRegister(Src0Reg, false, false, Src0Kill);
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/openbsd-current/gnu/llvm/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 4585 Register Src0Reg = getRegForValue(I->getOperand(0)); local 4586 if (!Src0Reg) 4595 Register QuotReg = fastEmitInst_rr(DivOpc, RC, Src0Reg, Src1Reg); 4599 Register ResultReg = fastEmitInst_rrr(MSubOpc, RC, QuotReg, Src1Reg, Src0Reg); 4644 Register Src0Reg = getRegForValue(Src0); local 4645 if (!Src0Reg) 4649 emitLSL_ri(VT, SrcVT, Src0Reg, ShiftVal, IsZExt); 4657 Register Src0Reg = getRegForValue(I->getOperand(0)); local 4658 if (!Src0Reg) 4665 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src1Re 4852 Register Src0Reg = getRegForValue(I->getOperand(0)); local [all...] |
/openbsd-current/gnu/llvm/llvm/lib/Target/Mips/ |
H A D | MipsFastISel.cpp | 1932 Register Src0Reg = getRegForValue(I->getOperand(0)); local 1934 if (!Src0Reg || !Src1Reg) 1937 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
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/openbsd-current/gnu/llvm/llvm/lib/CodeGen/GlobalISel/ |
H A D | LegalizerHelper.cpp | 6581 Register Src0Reg = MI.getOperand(1).getReg(); 6583 LLT SrcTy = MRI.getType(Src0Reg); 6587 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src0Reg).getReg(0); 6733 Register Src0Reg = MI.getOperand(1).getReg(); 6735 LLT Src0Ty = MRI.getType(Src0Reg); 6751 Val = Mask[0] == 0 ? Src0Reg : Src1Reg; 6770 BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg); 6773 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg;
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