Searched refs:Src0RC (Results 1 - 2 of 2) sorted by relevance
/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/ |
H A D | SIFixSGPRCopies.cpp | 357 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; local 359 Src0RC = MRI.getRegClass(MI.getOperand(1).getReg()); 362 (TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) {
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H A D | SIInstrInfo.cpp | 2069 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0); 2070 if (DstRC != Src0RC) { 2665 const TargetRegisterClass *Src0RC = Src0.isReg() ? 2669 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); 2671 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, 2682 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, 2720 const TargetRegisterClass *Src0RC = Src0.isReg() ? 2724 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); 2731 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, 2745 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, [all...] |
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