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/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonEarlyIfConv.cpp439 const MachineOperand &RO3 = I->getOperand(3); local
440 assert(RO1.isReg() && RO3.isReg());
442 if (RO1.getSubReg() != 0 || RO3.getSubReg() != 0) {
447 MachineInstr *Def3 = MRI->getVRegDef(RO3.getReg());

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