Searched refs:RHS2 (Results 1 - 4 of 4) sorted by relevance
| /freebsd-11.0-release/contrib/llvm/include/llvm/ADT/ |
| H A D | SparseBitVector.h | 231 // RHS1 & ~RHS2 into this element
233 const SparseBitVectorElement &RHS2,
239 Bits[i] = RHS1.Bits[i] & ~RHS2.Bits[i];
696 // Result of RHS1 & ~RHS2 is stored into this bitmap.
698 const SparseBitVector<ElementSize> &RHS2)
701 intersectWithComplement(RHS2);
703 } else if (this == &RHS2) {
704 SparseBitVector RHS2Copy(RHS2);
712 ElementListConstIter Iter2 = RHS2.Elements.begin();
715 // If RHS2 i
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| /freebsd-11.0-release/contrib/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSelect.cpp | 1068 Value *LHS, *RHS, *LHS2, *RHS2;
1103 if (SelectPatternFlavor SPF2 = matchSelectPattern(LHS, LHS2, RHS2).Flavor)
1104 if (Instruction *R = FoldSPFofSPF(cast<Instruction>(LHS),SPF2,LHS2,RHS2,
1107 if (SelectPatternFlavor SPF2 = matchSelectPattern(RHS, LHS2, RHS2).Flavor)
1108 if (Instruction *R = FoldSPFofSPF(cast<Instruction>(RHS),SPF2,LHS2,RHS2,
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| /freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 3863 SDValue RHS1, RHS2; local
3865 expandf64Toi32(RHS, DAG, RHS1, RHS2);
3867 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
3871 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
8102 unsigned RHS2 = MI->getOperand(4).getReg(); local
8107 .addReg(LHS2).addReg(RHS2)
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| /freebsd-11.0-release/contrib/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 14475 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14482 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
18198 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
18205 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
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