Searched refs:RHS1 (Results 1 - 3 of 3) sorted by relevance
| /freebsd-11.0-release/contrib/llvm/include/llvm/ADT/ |
| H A D | SparseBitVector.h | 231 // RHS1 & ~RHS2 into this element
232 void intersectWithComplement(const SparseBitVectorElement &RHS1,
239 Bits[i] = RHS1.Bits[i] & ~RHS2.Bits[i];
696 // Result of RHS1 & ~RHS2 is stored into this bitmap.
697 void intersectWithComplement(const SparseBitVector<ElementSize> &RHS1,
700 if (this == &RHS1) {
705 intersectWithComplement(RHS1, RHS2Copy);
711 ElementListConstIter Iter1 = RHS1.Elements.begin();
714 // If RHS1 is empty, we are done
715 // If RHS2 is empty, we still have to copy RHS1
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| /freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 3863 SDValue RHS1, RHS2; local
3865 expandf64Toi32(RHS, DAG, RHS1, RHS2);
3871 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
8101 unsigned RHS1 = MI->getOperand(3).getReg(); local
8105 .addReg(LHS1).addReg(RHS1));
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| /freebsd-11.0-release/contrib/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 14474 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14481 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
18197 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
18204 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
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