Searched refs:RC1 (Results 1 - 6 of 6) sorted by relevance
| /freebsd-11.0-release/contrib/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 1859 CodeGenRegisterClass *RC1 = RC; local
1861 if (RC1 == RC2)
1864 // Compute the set intersection of RC1 and RC2.
1865 const CodeGenRegister::Vec &Memb1 = RC1->getMembers();
1876 // If RC1 and RC2 have different spill sizes or alignments, use the
1877 // larger size for sub-classing. If they are equal, prefer RC1.
1878 if (RC2->SpillSize > RC1->SpillSize ||
1879 (RC2->SpillSize == RC1->SpillSize &&
1880 RC2->SpillAlignment > RC1->SpillAlignment))
1881 std::swap(RC1, RC
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| /freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenInsert.cpp | 318 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); local
319 uint16_t W1 = RC1.width(), W2 = RC2.width();
321 const BitTracker::BitValue &V1 = RC1[i], &V2 = RC2[i];
336 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1); local
338 uint16_t W1 = RC1.width(), W2 = RC2.width();
352 const BitTracker::BitValue &V1 = RC1[Bit1], V2 = RC2[Bit2];
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| H A D | HexagonBitSimplify.cpp | 160 static bool isEqual(const BitTracker::RegisterCell &RC1, uint16_t B1,
271 bool HexagonBitSimplify::isEqual(const BitTracker::RegisterCell &RC1, argument
275 // If RC1[i] is "bottom", it cannot be proven equal to RC2[i].
276 if (RC1[B1+i].Type == BitTracker::BitValue::Ref && RC1[B1+i].RefI.Reg == 0)
281 if (RC1[B1+i] != RC2[B2+i])
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| /freebsd-11.0-release/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | scorpion_reg_map.h | 1142 volatile u_int32_t RC1[118]; /* 0x1200 - 0x13d8 */ member in struct:svd_reg
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| H A D | ar9300reg.h | 2537 #define AR_RC1_0 AR_SVD_OFFSET(RC1)
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| H A D | osprey_reg_map.h | 1907 volatile u_int32_t RC1[118]; /* 0x11200 - 0x113d8 */ member in struct:svd_reg
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