Searched refs:ProcIndices (Results 1 - 3 of 3) sorted by relevance
/freebsd-11.0-release/contrib/llvm/utils/TableGen/ |
H A D | CodeGenSchedule.cpp | 497 SchedClasses.back().ProcIndices.push_back(0); 508 IdxVec ProcIndices(1, 0); 510 unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, ProcIndices); 534 if (SC.ProcIndices[0] != 0) 538 IdxVec ProcIndices; 540 ProcIndices.push_back(0); 545 ProcIndices.push_back(0); 558 ProcIndices.push_back(ProcModel.Index); 572 if (!std::count(ProcIndices.begin(), ProcIndices [all...] |
H A D | CodeGenSchedule.h | 99 IdxVec ProcIndices; member in struct:llvm::CodeGenSchedTransition 109 /// Writes and ReadDefs are empty. ProcIndices contains 0 for any processor. 113 /// subtargets. ProcIndices contains 0 for any processor. 117 /// instructions to this class. ProcIndices contains all the processors that 122 /// resolved at runtime. ProcIndices contains the set of processors that may 123 /// require the class. ProcIndices are propagated through SchedClasses as 135 IdxVec ProcIndices; member in struct:llvm::CodeGenSchedClass 367 ArrayRef<unsigned> ProcIndices); 403 unsigned FromClassIdx, ArrayRef<unsigned> ProcIndices); 415 ArrayRef<unsigned> ProcIndices); [all...] |
H A D | SubtargetEmitter.cpp | 831 if (TI->ProcIndices[0] == 0) { 835 IdxIter PIPos = std::find(TI->ProcIndices.begin(), 836 TI->ProcIndices.end(), ProcModel.Index); 837 if (PIPos != TI->ProcIndices.end()) { 849 // If ProcIndices contains 0, this class applies to all processors. 850 assert(!SCI->ProcIndices.empty() && "expect at least one procidx"); 851 if (SCI->ProcIndices[0] != 0) { 852 IdxIter PIPos = std::find(SCI->ProcIndices.begin(), 853 SCI->ProcIndices.end(), ProcModel.Index); 854 if (PIPos == SCI->ProcIndices 1302 IdxVec ProcIndices; local [all...] |
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