Searched refs:LE_CSR0 (Results 1 - 6 of 6) sorted by relevance

/freebsd-11.0-release/sys/dev/le/
H A Dam7990.c403 isr = (*sc->sc_rdcsr)(sc, LE_CSR0);
421 (*sc->sc_wrcsr)(sc, LE_CSR0, isr & ~(LE_C0_INEA | LE_C0_TDMD |
479 (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_INEA);
555 (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_INEA | LE_C0_TDMD);
585 if_printf(ifp, "status %04x\n", (*sc->sc_rdcsr)(sc, LE_CSR0));
608 if_printf(ifp, "status %04x\n", (*sc->sc_rdcsr)(sc, LE_CSR0));
H A Dam79900.c441 isr = (*sc->sc_rdcsr)(sc, LE_CSR0);
459 (*sc->sc_wrcsr)(sc, LE_CSR0, isr & ~(LE_C0_INEA | LE_C0_TDMD |
517 (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_INEA);
594 (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_INEA | LE_C0_TDMD);
624 if_printf(ifp, "status %04x\n", (*sc->sc_rdcsr)(sc, LE_CSR0));
646 if_printf(ifp, "status %04x\n", (*sc->sc_rdcsr)(sc, LE_CSR0));
H A Dlance.c261 (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_STOP);
287 (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_STOP);
317 (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_INIT);
321 if ((*sc->sc_rdcsr)(sc, LE_CSR0) & LE_C0_IDON)
324 if ((*sc->sc_rdcsr)(sc, LE_CSR0) & LE_C0_IDON) {
326 (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_INEA | LE_C0_STRT);
H A Dif_le_cbus.c235 le_cbus_wrcsr(sc, LE_CSR0, LE_C0_STOP);
237 if (le_cbus_rdcsr(sc, LE_CSR0) != LE_C0_STOP) {
H A Dif_le_isa.c220 le_isa_wrcsr(sc, LE_CSR0, LE_C0_STOP);
222 if (le_isa_rdcsr(sc, LE_CSR0) != LE_C0_STOP) {
H A Dlancereg.h140 #define LE_CSR0 0x0000 /* Control and status register */ macro

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