Searched refs:Ins (Results 1 - 25 of 60) sorted by relevance

123

/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/
H A DMipsCCState.h33 void PreAnalyzeCallResultForF128(const SmallVectorImpl<ISD::InputArg> &Ins,
50 PreAnalyzeFormalArgumentsForF128(const SmallVectorImpl<ISD::InputArg> &Ins);
93 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, argument
95 PreAnalyzeFormalArgumentsForF128(Ins);
96 CCState::AnalyzeFormalArguments(Ins, Fn);
101 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, argument
104 PreAnalyzeCallResultForF128(Ins, CLI);
105 CCState::AnalyzeCallResult(Ins, Fn);
H A DMipsCCState.cpp75 const SmallVectorImpl<ISD::InputArg> &Ins,
77 for (unsigned i = 0; i < Ins.size(); ++i) {
115 const SmallVectorImpl<ISD::InputArg> &Ins) {
117 for (unsigned i = 0; i < Ins.size(); ++i) {
123 if (Ins[i].Flags.isSRet()) {
129 assert(Ins[i].getOrigArgIndex() < MF.getFunction()->arg_size());
130 std::advance(FuncArg, Ins[i].getOrigArgIndex());
74 PreAnalyzeCallResultForF128( const SmallVectorImpl<ISD::InputArg> &Ins, const TargetLowering::CallLoweringInfo &CLI) argument
114 PreAnalyzeFormalArgumentsForF128( const SmallVectorImpl<ISD::InputArg> &Ins) argument
/freebsd-11.0-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.h44 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, argument
48 for (unsigned i = 0; i < Ins.size(); ++i)
52 for (unsigned i = 0; i < Ins.size(); ++i)
53 ArgIsShortVector.push_back(IsShortVectorType(Ins[i].ArgVT));
55 CCState::AnalyzeFormalArguments(Ins, Fn);
/freebsd-11.0-release/contrib/llvm/lib/CodeGen/
H A DCallingConvLower.cpp70 CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, argument
72 unsigned NumArgs = Ins.size();
75 MVT ArgVT = Ins[i].VT;
76 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
157 void CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, argument
159 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
160 MVT VT = Ins[i].VT;
161 ISD::ArgFlagsTy Flags = Ins[i].Flags;
/freebsd-11.0-release/contrib/llvm/lib/Transforms/Scalar/
H A DStraightLineStrengthReduce.cpp93 Stride(nullptr), Ins(nullptr), Basis(nullptr) {}
96 : CandidateKind(CT), Base(B), Index(Idx), Stride(S), Ins(I),
119 Instruction *Ins; member in struct:__anon3265::StraightLineStrengthReduce::Candidate
226 return (Basis.Ins != C.Ins && // skip the same instruction
229 Basis.Ins->getType() == C.Ins->getType() &&
231 DT->dominates(Basis.Ins->getParent(), C.Ins->getParent()) &&
290 return isGEPFoldable(cast<GetElementPtrInst>(C.Ins), TT
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H A DLoopInterchange.cpp91 Instruction *Ins = dyn_cast<Instruction>(I); local
92 if (!Ins)
352 bool areAllUsesReductions(Instruction *Ins, Loop *L);
603 bool LoopInterchangeLegality::areAllUsesReductions(Instruction *Ins, Loop *L) { argument
604 return !std::any_of(Ins->user_begin(), Ins->user_end(), [=](User *U) -> bool {
727 Instruction *Ins = dyn_cast<Instruction>(PHI->getIncomingValue(0));
728 if (!Ins)
732 if (!isa<PHINode>(Ins) && isOuterLoopExitBlock)
836 const Instruction &Ins
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/freebsd-11.0-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h135 const SmallVectorImpl<ISD::InputArg> &Ins,
142 const SmallVectorImpl<ISD::InputArg> &Ins,
149 const SmallVectorImpl<ISD::InputArg> &Ins,
156 const SmallVectorImpl<ISD::InputArg> &Ins,
H A DMSP430ISelLowering.cpp270 const SmallVectorImpl<ISD::InputArg> &Ins) {
271 State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack);
345 const SmallVectorImpl<ISD::InputArg> &Ins) {
346 State.AnalyzeCallResult(Ins, RetCC_MSP430);
370 &Ins,
381 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
383 if (Ins.empty())
396 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; local
412 Outs, OutVals, Ins, d
269 AnalyzeVarArgs(CCState &State, const SmallVectorImpl<ISD::InputArg> &Ins) argument
344 AnalyzeRetResult(CCState &State, const SmallVectorImpl<ISD::InputArg> &Ins) argument
366 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
422 LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
574 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
712 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
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/freebsd-11.0-release/contrib/llvm/lib/Target/BPF/
H A DBPFISelLowering.h57 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL,
68 const SmallVectorImpl<ISD::InputArg> &Ins,
H A DBPFISelLowering.cpp190 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
206 CCInfo.AnalyzeFormalArguments(Ins, CC_BPF64);
260 auto &Ins = CLI.Ins; local
382 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, CLI.DL, DAG,
437 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
445 if (Ins.size() >= 2) {
451 CCInfo.AnalyzeCallResult(Ins, RetCC_BPF64);
188 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
435 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
/freebsd-11.0-release/contrib/llvm/lib/Transforms/IPO/
H A DPartialInlining.cpp94 Instruction *Ins = &newReturnBlock->front(); local
99 PHINode *retPhi = PHINode::Create(OldPhi->getType(), 2, "", Ins);
101 Ins = newReturnBlock->getFirstNonPHI();
H A DIPConstantPropagation.cpp250 Instruction *Ins = cast<Instruction>(*I); local
257 if (ExtractValueInst *EV = dyn_cast<ExtractValueInst>(Ins))
270 Ins->replaceAllUsesWith(New);
271 Ins->eraseFromParent();
/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h709 const SmallVectorImpl<ISD::InputArg> &Ins,
765 const SmallVectorImpl<ISD::InputArg> &Ins,
776 const SmallVectorImpl<ISD::InputArg> &Ins,
783 const SmallVectorImpl<ISD::InputArg> &Ins,
811 const SmallVectorImpl<ISD::InputArg> &Ins,
817 const SmallVectorImpl<ISD::InputArg> &Ins,
823 const SmallVectorImpl<ISD::InputArg> &Ins,
838 const SmallVectorImpl<ISD::InputArg> &Ins,
848 const SmallVectorImpl<ISD::InputArg> &Ins,
857 const SmallVectorImpl<ISD::InputArg> &Ins,
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/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.cpp320 MachineBasicBlock::iterator Ins = MBB->begin(); local
322 if (Ins != MBB->end())
323 DL = Ins->getDebugLoc();
332 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
/freebsd-11.0-release/contrib/llvm/lib/Target/XCore/
H A DXCoreISelLowering.h150 const SmallVectorImpl<ISD::InputArg> &Ins,
158 const SmallVectorImpl<ISD::InputArg> &Ins,
212 const SmallVectorImpl<ISD::InputArg> &Ins,
/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h112 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
134 bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl,
144 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl,
H A DHexagonCommonGEP.cpp551 std::pair<NodeSymRel::iterator, bool> Ins = EqRel.insert(C); local
552 (void)Ins;
553 assert(Ins.second && "Cannot add a class");
583 std::pair<ProjMap::iterator,bool> Ins = PM.insert(std::make_pair(&S, Min)); local
584 (void)Ins;
585 assert(Ins.second && "Cannot add minimal element");
1258 ValueVect Ins; local
1260 Ins.push_back(&*I);
1261 for (ValueVect::iterator I = Ins.begin(), E = Ins
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/freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/
H A DSparcISelLowering.h114 const SmallVectorImpl<ISD::InputArg> &Ins,
120 const SmallVectorImpl<ISD::InputArg> &Ins,
126 const SmallVectorImpl<ISD::InputArg> &Ins,
/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.h38 const SmallVectorImpl<ISD::InputArg> &Ins,
H A DAMDGPUISelLowering.h114 const SmallVectorImpl<ISD::InputArg> &Ins,
117 const SmallVectorImpl<ISD::InputArg> &Ins) const;
/freebsd-11.0-release/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.h72 const SmallVectorImpl<ISD::InputArg> &Ins,
H A DWebAssemblyISelLowering.cpp342 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; local
343 if (Ins.size() > 1)
427 for (const auto &In : Ins) {
444 DAG.getNode(Ins.empty() ? WebAssemblyISD::CALL0 : WebAssemblyISD::CALL1,
446 if (Ins.empty()) {
500 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
511 for (const ISD::InputArg &In : Ins) {
498 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool , const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
/freebsd-11.0-release/contrib/llvm/utils/TableGen/
H A DCodeGenRegisters.h93 std::pair<CompMap::iterator, bool> Ins = local
104 return (Ins.second || Ins.first->second == B) ? nullptr
105 : Ins.first->second;
/freebsd-11.0-release/contrib/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h295 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
322 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
/freebsd-11.0-release/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp81 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
1058 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; local
1377 if (Ins.size() > 0) {
1436 Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, dl, MVT::i32), InFlag
1484 if (Ins.size() > 0) {
1606 assert(VTs.size() == Ins.size() && "Bad value decomposition");
1608 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
1628 LoadRetVTs.push_back(Ins[i].VT);
1643 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, Ins[
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